Volume 1, Number 1, January 2007

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  Nan Wang, Magdy A. Bayoumi: System-on-chip communication architecture: dynamic parallel fraction control bus design and test methodologies. 1-8
• 
  Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois: Optimised realisations of large integer multipliers and squarers using embedded blocks. 9-16
• 
  Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung: ROM to DSP block transfer for resource constrained synthesis. 17-26
• 
  Erik Larsson, Stina Edbom: Test data truncation for test quality maximisation under ATE memory depth constraint. 27-37
• 
  D. Adamidis, Haridimos T. Vergos: RNS multiplication/sum-of-squares units. 38-48
• 
  Haridimos T. Vergos, Costas Efstathiou: Design of efficient modulo 2ⁿ+1 multipliers. 49-57

Volume 1, Number 2, March 2007

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  Sohini Dasgupta, Alex Yakovle: Comparative analysis of GALS clocking schemes. 59-69
• 
  Peeter Ellervee, Jaan Raik, Kalle Tammemäe, Raimund Ubar: FPGA-based fault emulation of synchronous sequential circuits. 70-76
• 
  M. Amir Abas, Gordon Russell, David Kinniment: Embedded high-resolution delay measurement system using time amplification. 77-86
• 
  M. Amir Abas, Gordon Russell, David Kinniment: Built-in time measurement circuits - a comparative design study. 87-97
• 
  Dmitri Maslov, D. Michael Miller: Comparison of the cost metrics through investigation of the relation between optimal NCV and optimal NCT three-qubit reversible circuits. 98-104
• 
  Zhen Liu, Kai Zheng, Bin Liu: Hybrid cache architecture for high-speed packet processing. 105-112
• 
  Guadalupe Miñana, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar, Oscar Garnica, Sonia López: Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders. 113-119
• 
  Chantal Ykman-Couvreur, Vincent Nollet, Théodore Marescaux, Erik Brockmeyer, Francky Catthoor, Henk Corporaal: Design-time application mapping and platform exploration for MP-SoC customised run-time management. 120-128
• 
  Shiann-Rong Kuang, Jiun-Ping Wang: Design of power-efficient pipelined truncated multipliers with various output precision. 129-136
• 
  Simone Smorfa, Mauro Olivieri: HW-SW optimisation of JPEG2000 wavelet transform for dedicated multimedia processor architectures. 137-143

Volume 1, Number 3, May 2007

• 
  Christian Landrault, Erik Jan Marinissen: Editorial. 145
• 
  Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell: Fully digital test solution for a set of ADCs and DACs embedded in a SIP or SOC. 146-153
• 
  Bernd Laquai, Michael Braun, S. Walther, Guido Schulze: Flexible and scalable methodology for testing high-speed source synchronous interfaces on automated test equipment (ATE) with multiple fixed phase capture and compare. 154-158
• 
  Byoungho Kim, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham: Predicting mixed-signal dynamic performance using optimised signature-based alternate test. 159-169
• 
  Donghoon Han, Soumendu Bhattacharya, Abhijit Chatterjee: Low-cost parametric test and diagnosis of RF systems using multi-tone response envelope detection. 170-179
• 
  Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers: Deterministic logic BIST for transition fault testing. 180-186
• 
  Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli: Improving high-level and gate-level testing with FATE: A functional automatic test pattern generator traversing unstabilised extended FSM. 187-196
• 
  Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes: Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism. 197-206
• 
  Frank Poehl, Matthias Beck, Ralf Arnold, Jan Rzeha, Thomas Rabenalt, Michael Gössel: On-chip evaluation, compensation and storage of scan diagnosis data. 207-212
• 
  Gefu Xu, Adit D. Singh: Scan cell design for launch-on-shift delay tests with slow scan enable. 213-219
• 
  Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi: Enhancing delay fault coverage through low-power segmented scan. 220-229
• 
  Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez: Efficient testing and diagnosis of faulty power switches in SOCs. 230-236
• 
  Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: March AB, a state-of-the-art march test for realistic static linked faults and dynamic faults in SRAMs. 237-245
• 
  Yu-Jen Huang, Jin-Fu Li: Testing ternary content addressable memories with active neighbourhood pattern-sensitive faults. 246-255
• 
  Qiang Xu, Baosheng Wang, André Ivanov, Fung Yu Young: Test scheduling for built-in self-tested embedded SRAMs with data retention faults. 256-264

Volume 1, Number 4, July 2007

• 
  Philip Heng Wai Leong, Andreas Koch, Eduardo Boemo: Editorial - Field-programmable logic and applications. 265-266
• 
  Yan Lin, Mike Hutton, Lei He: Statistical placement for FPGAs considering. 267-275
• 
  Love Singhal, Elaheh Bozorgzadeh: Multi-layer floorplanning for reconfigurable designs. 276-294
• 
  Klaus Danne, Roland Mühlenbernd, Marco Platzner: Server-based execution of periodic tasks on dynamically reconfigurable hardware. 295-302
• 
  Nastaran Baradaran, Pedro C. Diniz: Exploiting parallelism in configurable architectures through custom array mapping. 303-311
• 
  David B. Thomas, Wayne Luk: Non-uniform random number generation through piecewise linear approximations. 312-321
• 
  Mohammad Hosseinabady, Pejman Lotfi-Kamran, Fabrizio Lombardi, Zainalabedin Navabi: Low overhead DFT using CDFG by modifying controller. 322-333
• 
  Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir: Optimising power efficiency in trace cache fetch unit. 334-348
• 
  Kuen Hung Tsoi, K. H. Leung, Philip Heng Wai Leong: High performance physical random number generator. 349-352
• 
  Irith Pomeranz, Sudhakar M. Reddy: Worst-case and average-case analysis of n-detection test sets and test generation strategies. 353-363
• 
  Aiman El-Maleh, S. Saqib Khursheed: Efficient test compaction for combinational circuits based on Fault detection count-directed clustering. 364-368
• 
  Myung-Hoon Yang, Youbean Kim, Youngkyu Park, D. Lee, Sungho Kang: Deterministic built-in self-test using split linear feedback shift register reseeding for low-power testing. 369-376
• 
  Ghassem Jaberipur, Amir Kaivani: Binary-coded decimal digit multipliers. 377-381
• 
  Guowu Yang, Xiaoyu Song, Marek A. Perkowski, William N. N. Hung, Jacob D. Biamonte, Zhiwei Tang: Four-level realisation of 3-qubit reversible functions. 382-388
• 
  Adnan Abdul-Aziz Gutub: High speed hardware architecture to compute galois fields GF(p) montgomery inversion with scalability features. 389-396
• 
  Bidyut Gupta, Shahram Rahimi, Ziping Liu: Novel low-overhead roll-forward recovery scheme for distributed systems. 397-404
• 
  Frank P. Burns, Julian P. Murphy, Delong Shang, Albert Koelmans, A. Yakorlev: Dynamic global security-aware synthesis using SystemC. 405-413
• 
  K.-J. Cho, J.-G. Chung: Low error fixed-width two's complement squarer design using Booth-folding technique. 414-422
• 
  Bhaskar Pal, Arnab Sinha, Pallab Dasgupta, P. P. Chakrabarti, Kaushik De: Hardware accelerated constrained random test generation. 423-433
• 
  J. H. Park, Y. Chu: Finite state machine-based DRAM power management with early resynchronisation. 434-442

Volume 1, Number 5, September 2007

• 
  Eduardo Peña, Eduardo de la Torre, Angel de Castro, Teresa Riesgo: A digital system to emulate wireless networks. 444-450
• 
  L. Garcia, Gustavo Marrero Callicó, D. Barreto, Víctor Reyes, Tomás Bautista, Antonio Núñez: Towards a configurable SoC MPEG-4 advanced simple profile decoder. 451-460
• 
  Miguel Lino Silva, João Canas Ferreira: Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems. 461-471
• 
  Ricardo Chaves, Leonel Sousa: Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures. 472-480
• 
  Bartomeu Alorda, Ivan de Paúl, Jaume Segura: Charge-based testing BIST for embedded memories. 481-490
• 
  Marcelino B. Santos, João Paulo Teixeira: Functional-oriented mask-based built-in self-test. 491-498
• 
  Peter R. Wilson, H. Alan Mantooth, P. Schwartz: Editorial Advances in Electronics Systems Simulation. 499-500
• 
  Won-Jong Lee, Woo-Chan Park, Vason P. Srini, Tack-Don Han: Simulation and development environment for mobile 3D graphics architectures. 501-507
• 
  Khalil Arshak, Essa Jafer, Declan McDonagh, Christian Ibala: Modelling and simulation of wireless sensor system for health monitoring using HDL and Simulinkw mixed environment. 508-518
• 
  H. Alan Mantooth, A. Francis, W. Zheng, Yucheng Feng: Modelling tools built upon the hardware description language foundation. 519-527
• 
  Brian Otis, Simone Gambini, Rahul C. Shah, Dan Steingart, E. Quevy, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli, Paul K. Wright: Modelling and simulation techniques for highly integrated, low-power wireless sensor networks. 528-536
• 
  Irith Pomeranz, Sudhakar M. Reddy: Effectiveness of scan-based delay fault tests in diagnosis of transition faults. 537-545
• 
  Zhonghai Lu, Axel Jantsch: Admitting and ejecting flits in wormhole-switched networks on chip. 546-556
• 
  Rafael A. Arce-Nazario, Manuel Jiménez, Domingo Rodríguez: Algorithmic-level exploration of discrete signal transforms for partitioning to distributed hardware architectures. 557-564
• 
  Elena Perez Ramo, Javier Resano, Daniel Mozos, Francky Catthoor: Memory hierarchy for high-performance and energyaware reconfigurable systems. 565-571
• 
  Derek Chi-Wai Pao, Peng Zhou, Bin Liu, Xin Zhang: Enhanced prefix inclusion coding filter-encoding algorithm for packet classification with ternary content addressable memory. 572-580
• 
  Tze-Yun Sung, Hsi-Chin Hsin: Design and simulation of reusable IP CORDIC core for special-purpose processors. 581-589
• 
  Feng Wang, Michael DeBole, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: On-chip bus thermal analysis and optimisation. 590-599
• 
  Saraju P. Mohanty, Elias Kougianos, Nagarajan Ranganathan: VLSI architecture and chip for combined invisible robust and fragile watermarking. 600-611
• 
  Chong-Fatt Law, Bah-Hwee Gwee, Joseph Sylvester Chang: Fast and memory-efficient invariant computation of ordinary Petri nets. 612-624
• 
  Hadi Parandeh-Afshar, Mohsen Saneei, Ali Afzali-Kusha, Massoud Pedram: Fast INC-XOR codec for low-power address buses. 625-626
• 
  Abdurazzag Sulaiman Almiladi, M. K. Ibrahim, M. Al Akidi, A. Aggoun: High-performance scalable bidirectional mixed radix-2 ⁿ serial-serial multipliers. 632-639
• 
  Lasse Harju, Jari Nurmi: Hardware platform for software-defined WCDMA/OFDM baseband receiver implementation. 640-652
• 
  Ahmad A. Al-Yamani: Energy-delay efficient test. 653-658

Volume 1, Number 6, November 2007

• 
  Erik Jan Marinissen, Nicola Nicolici: Editorial Silicon Debug and Diagnosis. 659-660
• 
  Nikolaos G. Bartzoudis, Andrew B. T. Hopkins, Klaus D. McDonald-Maier: Monitoring field-programmable gate array-based processing engines of dependable computer systems. 661-668
• 
  Marc Boule, Jean-Samuel Chenard, Zeljko Zilic: Debug enhancements in assertion-checker generation. 669-677
• 
  Bart Vermeulen, Sjaak Bakker: Debug architecture for the En-II system chip. 678-684
• 
  Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud: Extending gate-level diagnosis tools to CMOS intra-gate faults. 685-693
• 
  Yassine Hariri, Claude Thibeault: Bridging fault diagnostic tool based on DIDDQ probabilistic signatures, circuit layout parasitics and logic errors. 694-705
• 
  Chao-Wen Tzeng, J.-J. Hsu, Shi-Yu Huang: Robust paradigm for diagnosing hold-time faults in scan chains. 706-715
• 
  Yen-Lin Peng, Cheng-Wen Wu, Jing-Jia Liou, Chih-Tsun Huang: BIST-based diagnosis scheme for field programmable gate array interconnect delay faults. 716-723

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