Volume 12, Numbers 1-2, February 1998

• 
  Vishwani D. Agrawal: Editorial. 5
• 
  Michael Nicolaidis, Yervant Zorian: On-Line Testing for VLSI - A Compendium of Approaches. 7-20
• 
  J. J. Stiffler: On-Line Fault Monitoring. 21-27
• 
  Ricardo de Oliveira Duarte, Michael Nicolaidis, Hakim Bederr, Yervant Zorian: Efficient Totally Self-Checking Shifter Design. 29-39
• 
  V. V. Saposhnikov, A. A. Morosov, Vl. V. Saposhnikov, Michael Gössel: A New Design Method for Self-Checking Unidirectional Combinational Circuits. 41-53
• 
  Antonis M. Paschalis, Dimitris Gizopoulos, Nikolaos Gaitanis: Concurrent Delay Testing in Totally Self-Checking Systems. 55-61
• 
  Stanislaw J. Piestrak: Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters. 63-68
• 
  Dimitris Nikolos: Self-Testing Embedded Two-Rail Checkers. 69-79
• 
  Vladimir Székely, Márta Rencz, Jean-Michel Karam, Marcelo Lubaszewski, Bernard Courtois: Thermal Monitoring of Self-Checking Systems. 81-92
• 
  Karim Arabi, Bozena Kaminska: Integrated Temperature Sensors for On-Line Thermal Monitoring of Microelectronic Structures. 93-99
• 
  Eugeni García-Moreno, Benjamín Iñíguez, Miquel Roca, Jaume Segura, Eugeni Isern: Clocked Dosimeter Compatible with Digital CMOS Technology. 101-110
• 
  Hussain Al-Asaad, John P. Hayes, Brian T. Murray: Scalable Test Generators for High-Speed Datapath Circuits. 111-125
• 
  Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig: Mixed-Mode BIST Using Embedded Processors. 127-138
• 
  Piero Olivo, Marcello Dalpasso: A Bist Scheme for Non-Volatile Memories. 139-144
• 
  Alex Orailoglu: On-Line Fault Resilience Through Gracefully Degradable ASICs. 145-151
• 
  Y. Levendel: Delivering Dependable Telecommunication Services Using Off-the-Shelf System Components. 153-159

Volume 12, Number 3, June 1998

• 
  Vishwani D. Agrawal: Editorial. 167
• 
  Chouki Aktouf, Chantal Robach, A. Marinescu, Guy Mazaré: An Implementation Approach of the IEEE 1149.1 for the Routing Test of a VLSI Massively Parallel Architecture. 171-185
• 
  J. Yeandel, D. Thulborn, S. Jones: The Design and Implementation of an On-Line Testable UART. 187-198
• 
  Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar: Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems. 199-216
• 
  Zohair Sahraoui, Francky Catthoor, Paul Six, Hugo De Man: Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation. 217-238
• 
  Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas: Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits. 239-254
• 
  De-Qiang Wang, Lian-Chang Zhao: Combinatorial Analysis of Check Set Construction for Algorithm-Based Fault Tolerance Systems. 255-260

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