EURASIP Journal on Embedded Systems, Volume 2009
Volume 2009, 2009
- Haohuan Fu, William G. Osborne, Robert G. Clapp, Oskar Mencer, Wayne Luk: Accelerating Seismic Computations Using Customized Number Representations on FPGAs.
- Marcos R. Frankowiak, Roger I. Grosvenor, Paul W. Prickett: Microcontroller-Based Process Monitoring Using Petri-Nets.
- Martin Schoeberl: Time-Predictable Computer Architecture.
- Emi Mathews, Axel Poigné: Evaluation of a "Smart" Pedestrian Counting System Based on Echo State Networks.
- Ben Cordes, Miriam Leeser: Parallel Backprojection: A Case Study in High-Performance Reconfigurable Computing.
- Ralf Seepold, Natividad Martínez Madrid, Jesús Sáez Gómez-Escalonilla, Alvaro Reina Nieves: An Embedded Software Platform for Distributed Automotive Environment Management.
- Ákos Lédeczi, János Sallai, Péter Völgyesi, Ryan Thibodeaux: Differential Bearing Estimation for RF Tags.
- Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz: A Formal Approach to the Verification of Networks on Chip.
- Stéphane Simard, Jean-Gabriel Mailloux, Rachid Beguenane: Prototyping Advanced Control Systems on FPGA.
- Raimund Kirner: Towards Preserving Model Coverage and Structural Code Coverage.
- Tiberiu Seceleanu, Ville Leppänen, Olli Nevalainen: Improving the Performance of Bus Platforms by Means of Segmentation and Optimized Resource Allocation.
- Cao Liang, Xin-Ming Huang: SmartCell: An Energy Efficient Coarse-Grained Reconfigurable Architecture for Stream-Based Applications.
- Robert Leidenfrost, Wilfried Elmenreich: Firefly Clock Synchronization in an 802.15.4 Wireless Network.
- Yongsoon Lee, Younhee Choi, Moon Ho Lee, Seok-Bum Ko: Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector.
- Wilfried Elmenreich, Markus Kucera, Bernhard Rinner, Ralf Seepold, Volker Turau: Challenges on Complexity and Connectivity in Embedded Systems.
- Simon Yuan, Li Hsien Yoong, Sidharta Andalam, Partha S. Roop, Zoran Salcic: A New Multithreaded Architecture Supporting Direct Execution of Esterel.
- Vinay Sriram, David Kearney: An FPGA Implementation of a Parallelized MT19937 Uniform Random Number Generator.
- Vinay Sriram, Miriam Leeser: FPGA Supercomputing Platforms, Architectures, and Techniques for Accelerating Computationally Complex Algorithms.
- Laszlo Hars: Random Number Generators in Secure Disk Drives.
- Heikki Hurskainen, Jussi Raasakka, Tapani Ahonen, Jari Nurmi: Multicore Software-Defined Radio Architecture for GNSS Receiver Signal Processing.
- Khalil Khattab, Julien Dubois, Johel Mitéran: Cascade Boosting-Based Object Detection from High-Level Description to Hardware Implementation.
- Baofeng Li, Yong Dou, Haifang Zhou, Xingming Zhou: FPGA Accelerator for Wavelet-Based Automated Global Image Registration.
- Yifeng Qiu, Wael M. Badawy: A Prototyping Virtual Socket System-On-Platform Architecture with a Novel ACQPPS Motion Estimator for H.264 Video Encoding Applications.
- Sonia Khatchadourian, Jean-Christophe Prévotet, Lounis Kessal: Hardware Architecture for Pattern Recognition in Gamma-Ray Experiment.
- Tero Arpinen, Erno Salminen, Timo D. Hämäläinen, Marko Hännikäinen: Performance Evaluation of UML2-Modeled Embedded Streaming Applications with System-Level Simulation.
- Massimo Rovini, Giuseppe Gentile, Francesco Rossi, Luca Fanucci: Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes.
- Marco Antonio López Trinidad, Maurizio Valle: Reliable Event Detectors for Constrained Resources Wireless Sensor Node Hardware.
- Lee Seng Yeong, Christopher Wing Hong Ngau, Li-Minn Ang, Kah Phooi Seng: Efficient Processing of a Rainfall Simulation Watershed on an FPGA-Based Architecture with Fast Access to Neighbourhood Pixels.
- Maxime Pelcat, Jonathan Piat, Matthieu Wipliez, Slaheddine Aridhi, Jean-François Nezan: An Open Framework for Rapid Prototyping of Signal Processing Applications.
- Li Wern Chew, Wai Chong Chia, Li-Minn Ang, Kah Phooi Seng: Very Low-Memory Wavelet Compression Architecture Using Strip-Based Processing for Implementation in Wireless Sensor Networks.
- Samuel Garcia, Bertrand Granado: OLLAF: A Fine Grained Dynamically Reconfigurable Architecture for OS Support.
- Fakhreddine Ghaffari, Benoit Miramond, François Verdier: Run-Time HW/SW Scheduling of Data Flow Applications on Reconfigurable Architectures.
- Muhammad Yasir Qadri, Klaus D. McDonald-Maier: Data Cache-Energy and Throughput Models: Design Exploration for Embedded Processors.
- Anthony Kolar, Olivier Romain, Jade Ayoub, David Faura, Sylvain Viateur, Bertrand Granado, Tarik Graba: A System for an Accurate 3D Reconstruction in Video Endoscopy Capsule.
- Obianuju Ndili, Tokunbo Ogunfunmi: FPSoC-Based Architecture for a Fast Motion Estimation Algorithm in H.264/AVC.
- Linlin Zhang, Virginie Fresse, Mohammed A. S. Khalid, Dominique Houzet, Anne-Claire Legrand: Evaluation and Design Space Exploration of a Time-Division Multiplexed NoC on FPGA for Image Analysis Applications.
- Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary: Comments on "Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes".
- Massimo Rovini, Giuseppe Gentile, Francesco Rossi, Luca Fanucci: Reply to "Comments on Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes".
- Jehangir Khan, Smaïl Niar, Mazen A. R. Saghir, Yassin Elhillali, Atika Rivenq-Menhaj: Trade-Off Exploration for Target Tracking Application in a Customized Multiprocessor Architecture.
- Markus Rupp, Ahmet T. Erdogan, Bertrand Granado: Design and Architectures for Signal and Image Processing.
- Ke Xu, Oliver Chiu-sing Choy: Low-Power Bitstream-Residual Decoder for H.264/AVC Baseline Profile Decoding.
- Huda S. Muhammad, Assim Sagahyroon: Virtual Prototyping and Performance Analysis of Two Memory Architectures.
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2014-07-10T213129 by the dblp team