Volume 20, Number 1, January/February 2003

EIC Message

• 
  Rajesh Gupta: From the Editor in Chief: Twenty years! 1-

Features

• 
  Alex Orailoglu, Alexander V. Veidenbaum: Guest Editors' Introduction: Application-Specific Microprocessors. 6-7
• 
  Wolfgang Raab, Nico Brüls, J. A. Ulrich Hachmann, Jens Harnisch, Ulrich Ramacher, Christian Sauer, Axel Techmer: A 100-GOPS Programmable Processor for Vehicle Vision Systems. 8-16
• 
  Peter Petrov, Alex Orailoglu: Application-Specific Instruction Memory Customizations for Power-Efficient Embedded Processors. 18-25
• 
  Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt: Compilation Approach for Coarse-Grained Reconfigurable Architectures. 26-33
• 
  Oliver Wahlen, Manuel Hohenauer, Rainer Leupers, Heinrich Meyr: Instruction Scheduler Generation for Retargetable Compilation. 34-41

Special Features

• 
  Jörg E. Vollrath: Testing and Characterization of SDRAMs. 42-50
• 
  Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski: 2D Test Sequence Generators. 51-59
• 
  Florence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei: An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs. 60-67
• 
  Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne: Design Techniques for EEPROMs Embedded in Portable Systems on Chips. 68-75
• 
  Luigi Carro, Marcelo Negreiros, Gabriel Parmegiani Jahn, Adão Antônio de Souza Jr., Denis Teixeira Franco: Circuit-Level Considerations for Mixed-Signal Programmable Components. 76-84

The Road Ahead

• 
  Andrew B. Kahng: Error Tolerance. 86-87

Panel Summarie

• 
  Carol Stolicny: ITC 2002 Panels. 88-90

Standards

• 
  Peter J. Ashenden: Boundary Scan Test Standards. 91-92

Conference Reports

• 
  Ahmed Amine Jerraya: Hot Topics at HLDVT 02. 92-

Newsletters

• 
  DATC Newsletter. 93-
• 
  TTTC Newsletter. 94-95

The Last Byte

• 
  Frank Vahid: Making the Best of Those Extra Transistors. 96-

Volume 20, Number 2, March/April 2003

EIC Message

• 
  Rajesh Gupta: From the Editor in Chief: Full Circle? 1-

Features

• 
  Monica Lobetti Bodoni, Ben Bennetts: Guest Editors' Introduction: Board Test. 5-7
• 
  Erik Jan Marinissen, Bart Vermeulen, Henk D. L. Hollmann, Ben Bennetts: Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint. 8-18
• 
  Bradford G. Van Treuren, José M. Miranda: Embedded Boundary Scan. 20-25
• 
  Mahnaz Salamati, Dag Stranneby: Electromagnetic Signatures as a Tool for Connectionless Test. 26-30
• 
  Uros Kac, Franc Novak, Florence Azaïs, Pascal Nouet, Michel Renovell: Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test. 32-39

Special Features

• 
  Nur Engin, Hans G. Kerkhoff: Fast Fault Simulation for Nonlinear Analog Circuits. 40-47
• 
  Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou: A Design-for-Verification Technique for Functional Pattern Reduction. 48-55
• 
  Miroslav Cupák, Francky Catthoor, Hugo De Man: Efficient System-Level Functional Verification Methodology for Multimedia Applications. 56-64
• 
  João M. P. Cardoso, Horácio C. Neto: Compilation for FPGA-Based Reconfigurable Hardware. 65-75

Round Table

• 
  Test Data Compression. 76-87

Conference Reports

• 
  Conference Reports. 88-89

Panel Summaries

• 
  Carol Stolicny: ITC 2002 Panels: Part 2. 90-91

Newsletters

• 
  DATC Newsletter. 93-
• 
  TTTC Newsletter. 94-95

The Last Byte

• 
  Kenneth P. Parker: Testing for what? 96-

Volume 20, Number 3, May/June 2003

EIC Message

• 
  Rajesh Gupta: From the Editor in Chief: A "Powerful" Issue! 1-

Features

• 
  Sani R. Nassif, Soha Hassoun: Guest Editors' Introduction: On-Chip Power Distribution Networks. 5-6
• 
  Sachin S. Sapatnekar, Haihua Su: Analysis and Optimization of Power Grids. 7-15
• 
  Rajendran Panda, Savithri Sundareswaran, David Blaauw: Impact of Low-Impedance Substrate on Power Supply Integrity. 16-22
• 
  Hui Zheng, Byron Krauter, Lawrence T. Pileggi: Electrical Modeling of Integrated-Package Power and Ground Distributions. 24-31
• 
  Arindam Mukherjee, Malgorzata Marek-Sadowska: Clock and Power Gating with Timing Closure. 32-39
• 
  Ed Grochowski, David Ayers, Vivek Tiwari: Microarchitectural dI/dt Control. 40-47

Special Infrastructure IP Section

• 
  Yervant Zorian: Guest Editor's Introduction: Advances in Infrastructure IP. 49-
• 
  Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: Online Self-Repair of FIR Filters. 50-57
• 
  Yervant Zorian, Samvel K. Shoukourian: Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield. 58-66
• 
  Md. Saffat Quasem, Zhigang Jiang, Sandeep K. Gupta: Benefits of a SoC-Specific Test Methodology. 68-77
• 
  C. J. Clark, Mike Ricchetti: Infrastructure IP for Configuration and Test of Boards and Systems. 78-87

DAC Watch

• 
  Luciano Lavagno, Limor Fix: DAC Highlights. 88-89
• 
  Alberto L. Sangiovanni-Vincentelli: DAC Turns 40! 90-96
• 
  Pat O. Pistilli: DAC: Serving the EDA Community for 40 Years. 97-98
• 
  Ronald A. Rohrer: DAC, Moore's Law Still Drive EDA. 99-100
• 
  Giovanni De Micheli: CASS Brings Publishing to Its DAC Partnership. 101-102

Special Report: CADathlon

• 
  Soha Hassoun, Geert Janssen: First CADathlon Programming Contest held at 2002 ICCAD. 104-107

DTAP Update

• 
  Yervant Zorian: IEEE CASS becomes D&T Copublisher. 108-

The Road Ahead

• 
  Andrew B. Kahng: Bringing down NRE. 110-111

Standards

• 
  Peter J. Ashenden: VHDL-200X: The Next Revision. 112-113

Panel Summaries

• 
  Tom Anderson: Who Cares about System Verification? 114-

Conference Reports

• 
  Conference Reports. 115-

Newsletters

• 
  TTTC Newsletter. 116-117
• 
  DATC Newsletter. 118-

The Last Byte

• 
  Mary Jane Irwin: Power-Aware Designers at Odds with Power Grid Designers? 120-

Volume 20, Number 4, July/August 2003

EIC Message

• 
  Rajesh Gupta: From the Editor in Chief: Addressing Problems of the Large. 3-

Special Features

• 
  Ravi Hosabettu, Ganesh Gopalakrishnan, Mandayam K. Srivas: A Practical Methodology for Verifying Pipelined Microarchitectures. 4-14
• 
  João P. Marques Silva, Luís Guerra e Silva: Solving Satisfiability in Combinational Circuits. 16-21
• 
  Ozgur Sinanoglu, Alex Orailoglu: Compacting Test Responses for Deeply Embedded SoC Cores. 22-30
• 
  Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian: A Hierarchical Infrastructure for SoC Test Management. 32-39
• 
  Ian G. Harris: Fault Models and Test Generation for Hardware-Software Covalidation. 40-47
• 
  Nicola Nicolici, Bashir M. Al-Hashimi: Power-Conscious Test Synthesis and Scheduling. 48-55
• 
  Dionisios N. Pnevmatikatos, Ioannis Sourdis, Kyriakos Vlachos: An Efficient, Low-Cost I/O Subsystem for Network Processors. 56-64

Roundtable

• 
  Embedded Memories for the Future. 66-81

Standards

• 
  David I. Rich: The Evolution of SystemVerilog. 82-84

Panel Summaries

• 
  Carl Pixley, Juan Antonio Carballo: Panel Summaries. 86-88

Conference Reports

• 
  McCluskey Awarded TTTC Lifetime Contribution Medal. 89-

Newsletters

• 
  TTTC Newsletter. 90-91
• 
  DATC Newsletter. 93-

The Last Byte

• 
  Bill Mann: Test's Evolving Mission. 95-96

Volume 20, Number 5, September/October 2003

From the EIC

• 
  Rajesh Gupta: At-Speed Testing: A Shared Red Brick between Design and Test. 1-

Feature

• 
  Kenneth M. Butler, Kwang-Ting (Tim) Cheng, Li-C. Wang: Guest Editors' Introduction: Speed Test and Speed Binning for Complex ICs. 6-7
• 
  Kee Sup Kim, Subhasish Mitra, Paul G. Ryan: Delay Defect Characteristics and Testing Strategies. 8-16
• 
  Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli: High-Frequency, At-Speed Scan Testing. 17-25
• 
  Stephen Pateras: Achieving At-Speed Structural Test. 26-33
• 
  Alfred L. Crouch, John C. Potter, Jason Doege: AC Scan Path Selection for Physical Debugging. 34-40
• 
  Bruce Cory, Rohit Kapur, Bill Underwood: Speed Binning with Path Delay Test in 150-nm Technology. 41-45
• 
  Robert Madge, Brady Benware, W. Robert Daasch: Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs. 46-53

ITC Watch

• 
  Robert C. Aitken, Gordon W. Roberts: ITC 2003: Breaking Test Interface Bottlenecks. 54-
• 
  Gordon W. Roberts, Robert C. Aitken: ITC Highlights. 55-57
• 
  Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian: Embedded Deterministic Test for Low-Cost Manufacturing. 58-66
• 
  Darren Anand, Bruce Cowan, Owen Farnsworth, Peter Jakobsen, Steven F. Oakland, Michael Ouellette, Donald L. Wheater: An On-Chip Self-Repair Calculation and Fusing Methodology. 67-75
• 
  Bill Eklow, Carl Barnhart, Kenneth P. Parker: IEEE 1149.6: A Boundary-Scan Standard for Advanced Digital Networks. 76-83
• 
  Peter C. Maxwell: Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings. 84-89
• 
  ARM Twisting with Sir Robin: An Interview with ARM Chairman Sir Robin Saxby. 90-93

Standards

• 
  Jay Lawrence: Orthogonality of Verilog Data Types and Object Kinds. 94-96

Conference Reports

• 
  Conference Reports. 97-99

Newsletters

• 
  DATC Newsletter. 100-
• 
  TTTC Newsletter. 102-103

The Last Byte

• 
  Scott Davidson: All I Know I Learned at ITC. 104-

Volume 20, Number 6, November/December 2003

From the EIC

• 
  Rajesh Gupta: From the EIC: The changing face of IC design and its industry. 1-

Features

• 
  Soha Hassoun, Yong-Bin Kim, Fabrizio Lombardi: Guest Editors' Introduction: Clockless VLSI Systems. 5-8
• 
  Alain J. Martin, Mika Nyström, Catherine G. Wong: Three Generations of Asynchronous Microprocessors. 9-17
• 
  Stephen H. Unger: Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors. 18-24
• 
  Satish K. Bandapati, Scott C. Smith, Minsu Choi: Design and Characterization of Null Convention Self-Timed Multipliers. 26-36
• 
  Steve Masteller, Lief Sorenson: Cycle Decomposition in NCL. 38-43
• 
  Juha Plosila, Tiberiu Seceleanu, Pasi Liljeberg: Implementation of a Self-Timed Segmented Bus. 44-50
• 
  Woo Jin Kim, Yong-Bin Kim: Automating Wave-Pipelined Circuit Design. 51-58

Special Section: Perspectives in EDA

• 
  Alberto L. Sangiovanni-Vincentelli: The Tides of EDA. 59-75
• 
  Fabless or IDM? What the Future Holds for Both: An Interview with Cirrus Logic Chairman, Michael L. Hackworth. 76-85
• 
  What Is the Next Implementation Fabric? 86-95

The Road Ahead

• 
  Andrew B. Kahng: How much variability can designers tolerate? 96-97

Standards

• 
  Wolfgang Roethig: New advanced library format standard approved. 98-99

Panel Summaries

• 
  Eric Dupont, Grant Martin: Panel Summaries. 100-102

Conference Reports

• 
  Vladimir Hahanov, Raimund Ubar: Conference Reports. 103-

Newsletters

• 
  Test Technology TC Newsletter. 104-105
• 
  Design Automation Technical Committee Newsletter. 106-

Annual Index

• 
  2003 Annual Index IEEE Design & Test of Computers Volume 20. 108-119

The Last Byte

• 
  Suhwan Kim, Conrad H. Ziesler: A clockless future for systems on chip. 120-