Volume 19, Number 1, January/February 2002

• 
  EIC Message. 1-

• 
  News. 5-

• 
  Markus Rudack, Michael Redeker, Jörg Hilgenstock, Sören Moch, Jens Castagne: A Large-Area Integrated Multiprocessor System for Video Applications. 6-17
• 
  Chouki Aktouf: A Complete Strategy for Testing an On-Chip Multiprocessor Architecture. 18-28

• 
  Pranab K. Nag, Anne E. Gattiker, Sichao Wei, Ronald D. Blanton, Wojciech Maly: Modeling the Economics of Testing: A DFT Perspective. 29-41

• 
  Ismet Bayraktaroglu, Alex Orailoglu: Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BIST. 42-53
• 
  Jun Zhao, Fred J. Meyer, Fabrizio Lombardi: Analyzing and Diagnosing Interconnect Faults in Bus-Structured Systems. 54-64
• 
  Yi Cai, Bernd Laquai, Kent Luehman: Jitter Testing for Gigabit Serial Communication Transceivers. 66-74
• 
  Philippe Magarshack: Improving SoC Design Quality through a Reproducible Design Flow. 76-83

• 
  Verilog and Other Standards. 84-85

• 
  Conference Reports. 86-87

• 
  Panel Summaries. 88-90

• 
  New Products. 91-

• 
  TTTC Newsletter. 92-93

• 
  DATC Newsletter. 94-

• 
  The Last Byte. 96-

Volume 19, Number 2, March/April 2002

• 
  Deep-Submicron Challenges. 3-

• 
  Luis Miguel Silveira, Nuno Vargas: Characterizing Substrate Coupling in Deep-Submicron Designs. 4-15
• 
  Michele Favalli, Cecilia Metra: Online Testing Approach for Very Deep-Submicron ICs. 16-23
• 
  Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy: IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions. 24-33
• 
  Mircea R. Stan: CMOS Circuits with Subvolt Supply Voltages. 34-43
• 
  Chenn-Jung Huang, Chua-Chin Wang, Chi-Feng Wu: Image Processing Techniques for Wafer Defect Cluster Identification. 44-48
• 
  Carlos Galup-Montoro, Márcio C. Schneider, Rafael M. Coitinho: Resizing Rules for MOS Analog-Design Reuse. 50-58

• 
  Stephan Schulz II, Jerzy W. Rozenblit, Klaus Buchenrieder: Multilevel Testing for Design Verification of Embedded Systems. 60-69

• 
  Shared Red Bricks. 70-71

• 
  Standards. 72-73

• 
  Panel Summaries. 74-76

• 
  DATC Newsletter. 77-

• 
  TTTC Newsletter. 78-79

• 
  Yet Another Thiotimoline Application. 80-

Volume 19, Number 3, May/June 2002

• 
  Enabling IP. 1-

• 
  Guest Editor's Introduction: What is Infrastructure IP? 5-7
• 
  Teresa L. McLaurin, Souvik Ghosh: ETM10 Incorporates Hardware Segment of IEEE P1500. 8-13
• 
  Jim Bordelon, Ben Tranchina, Vipin Madangarli, Mark Craig: A Strategy for Mixed-Signal Yield Improvement. 14-23
• 
  Sassan Tabatabaei, André Ivanov: Embedded Timing Analysis: A SoC Infrastructure. 24-36
• 
  Bart Vermeulen, Sandeep Kumar Goel: Design for Debug: Catching Design Errors in Digital Chips. 37-45
• 
  Stephen Pateras: IP for Embedded Diagnosis. 46-55
• 
  Eric Dupont, Michael Nicolaidis, Peter Rohr: Embedded Robustness IPs for Transient-Error-Free ICs. 56-70

• 
  Andrew E. Caldwell, Igor L. Markov: Toward CAD-IP Reuse: A Web Bookshelf of Fundamental Algorithms. 72-81
• 
  Patrick Girard: Survey of Low-Power Testing of VLSI Circuits. 82-92
• 
  Alfredo Benso, Silvia Chiusano, Paolo Prinetto: DFT and BIST of a Multichip Module for High-Energy Physics Experiments. 94-105

• 
  Design and Test Education in Latin America. 106-113

• 
  Peter J. Ashenden: What Makes a Good Standard? 114-115

• 
  Adam Osseiran: Conference Reports. 116-

• 
  DATC Newsletter. 117-

• 
  TTTC Newsletter. 118-119

• 
  Andrew B. Kahng: Variability. 120, 116

Volume 19, Number 4, July/August 2002

• 
  Building a community. 3-

• 
  Peter Marwedel: Guest Editor's Introduction: Processor-Based Designs. 5-6
• 
  Dongkun Shin, Hojun Shim, Yongsoo Joo, Han-Saem Yun, Jihong Kim, Naehyuck Chang: Energy-Monitoring Tool for Low-Power Embedded Programs. 7-17
• 
  Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey: Embedded Software-Based Self-Test for Programmable Core-Based Designs. 18-27
• 
  Ing-Jer Huang, Chung-Fu Kao, Hsin-Ming Chen, Ching-Nan Juan, Tai-An Lu: A Retargetable Embedded In-Circuit Emulation Module for Microprocessors. 28-38
• 
  Martijn J. Rutten, Jos T. J. van Eijndhoven, Egbert G. T. Jaspers, Pieter van der Wolf, Evert-Jan D. Pol, Om Prakash Gangwal, Adwin H. Timmer: A Heterogeneous Multiprocessor Architecture for Flexible Media Processing. 39-50
• 
  Rainer Leupers: Compiler Design Issues for Embedded Processors. 51-58
• 
  Pierre G. Paulin, Miguel Santana: FlexWare: A Retargetable Embedded-Software Development Environment. 59-69

• 
  David Blaauw, Luciano Lavagno: Guest Editors' Introduction: Hot Topics at This Year's Design Automation Conference. 72-73
• 
  Michael H. Perrott: Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL Circuits. 74-83
• 
  Robert Siegmund, Dietmar Müller: Automatic Synthesis of Communication Controller Hardware from Protocol Specifications. 84-95
• 
  Kanna Shimizu, David L. Dill: Using Formal Specifications for Functional Validation of Hardware Designs. 96-106
• 
  Alex Kondratyev, Kelvin Lwin: Design of Asynchronous Circuits Using Synchronous CAD Tools. 107-117
• 
  Kanishka Lahiri, Sujit Dey, Anand Raghunathan: Communication-Based Power Management. 118-130

• 
  Aarti Gupta: Assertion-based verification turns the corner. 131-132

• 
  DATC Newsletter. 133-

• 
  Test Technology TC Newsletter. 134-135

• 
  The Cost of Design. 136, 135

Volume 19, Number 5, September/October 2002

• 
  Rajesh Gupta: Sustaining an Industry Obsession. 1-

• 
  Jaume Segura, Peter C. Maxwell: Guest Editors' Introduction: Defect-Oriented Testing in the Deep-Submicron Era. 5-7
• 
  Sagar S. Sabade, D. M. H. Walker: IDDQ Test: Will It Survive the DSM Challenge? 8-16
• 
  Rosa Rodríguez-Montañés, Paul Volf, José Pineda de Gyvez: Resistance Characterization for Weak Open Defects. 18-26
• 
  Xavier Aragonès, José Luis González, Francesc Moll, Antonio Rubio: Noise Generation and Coupling Mechanisms in Deep-Submicron ICs. 27-35
• 
  Ali Keshavarzi, James Tschanz, Siva Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins: Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. 36-43
• 
  Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich: High Defect Coverage with Low-Power Test Sequences in a BIST Environment. 44-52

• 
  Robert C. Aitken, Donald L. Wheater: Guest Editors' Introduction: Stressing the Fundamentals. 54-55
• 
  Shuo Sheng, Michael S. Hsiao: Efficient Sequential Test Generation Based on Logic Simulation. 56-64
• 
  Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Andrew Ferko, Brion L. Keller, David Scott, Bernd Könemann, Takeshi Onodera: Extending OPMISR beyond 10x Scan Test Efficiency. 65-72
• 
  W. Robert Daasch, James McNames, Robert Madge, Kevin Cota: Neighborhood Selection for IDDQ Outlier Screening at Wafer Sort. 74-81
• 
  Sule Ozev, Christian Olgaard, Alex Orailoglu: Multilevel Testability Analysis and Solutions for Integrated Bluetooth Transceivers. 82-91

• 
  Marcello Dalpasso, Alessandro Bogliolo, Luca Benini: Virtual Simulation of Distributed IP-Based Designs. 92-104

• 
  Formal Verification: Current Use and Future Perspectives. 105-113

• 
  Conference Reports. 114-115

• 
  Test Technology TC Newsletter. 116-117

• 
  Design Automation Technical Committee Newsletter. 118-

• 
  Krishnendu Chakrabarty, Erik Jan Marinissen: How Useful are the ITC 02 SoC Test Benchmarks? 120, 119

Volume 19, Number 6, November/December 2002

• 
  Grant Martin: Guest Editor's Introduction: The Reuse of Complex Architectures. 4-5
• 
  Andrew Mihal, Chidamber Kulkarni, Matthew W. Moskewicz, Mel M. Tsai, Niraj Shah, Scott J. Weber, Yujia Jin, Kurt Keutzer, Christian Sauer, Kees A. Vissers, Sharad Malik: Developing Architectural Platforms: A Disciplined Approach. 6-16
• 
  Pierre G. Paulin, Chuck Pilkington, Essaid Bensoudane: StepNP: A System-Level Exploration Platform for Network Processors. 17-26
• 
  Clifford Liem, Francois Breant, Sarveta Jadhav, Ray O'Farrell, Ray Ryan, Oz Levia: Embedded Tools for a Configurable and Customizable DSP Architecture. 27-35
• 
  Greg Stitt, Frank Vahid: Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic. 36-43
• 
  Vincent John Mooney III, Douglas M. Blough: A Hardware-Software Real-Time Operating System Framework for SoCs. 44-51
• 
  Wander O. Cesário, Damien Lyonnard, Gabriela Nicolescu, Yanick Paviot, Sungjoo Yoo, Ahmed Amine Jerraya, Lovic Gauthier, Mario Diaz-Nava: Multiprocessor SoC Platforms: A Component-Based Design Approach. 52-63

• 
  Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José Luis Huertas: Practical Oscillation-Based Test of Integrated Filters. 64-72
• 
  Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José Luis Huertas: Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macrocell. 73-82
• 
  Michel Renovell, Florence Azaïs, Yves Bertrand: Improving Defect Detection in Static-Voltage Testing. 83-89
• 
  Amit Chowdhary, Rajesh K. Gupta: A Methodology for Synthesis of Data Path Circuitse. 90-100

• 
  Rajesh Gupta: EIC Message: The Neglected Community. 3-
• 
  Conference Reports. 101-
• 
  Panel Summaries. 102-103
• 
  Andrew B. Kahng: The Road Ahead: The significance of packaging. 104-105
• 
  Peter J. Ashenden: Standards: Technical activities in Accellera. 106, 109
• 
  DATC Newsletter. 107-
• 
  TTTC Newsletter. 108-109
• 
  Annual Index. 110-119
• 
  The Last Byte. 120-

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