Volume 5,
Number 1,
January-June 2006
- Chuanjun Zhang:
Balanced instruction cache: reducing conflict misses of direct-mapped caches through balanced subarray accesses.
2-5
- Guilherme Ottoni, Ram Rangan, Adam Stoler, Matthew J. Bridges, David I. August:
From sequential programs to concurrent threads.
6-9
- Amit K. Gupta, William J. Dally:
Topology optimization of interconnection networks.
10-13
- Tomer Y. Morad, Uri C. Weiser, A. Kolodnyt, Mateo Valero, Eduard Ayguadé:
Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors.
14-17
- Nicholas Riley, Craig B. Zilles:
Probabilistic counter updates for predictor hysteresis and bias.
18-21
- Huiyang Zhou:
A case for fault tolerance and performance enhancement using chip multi-processors.
22-25
- Moon-Sang Lee, Sang-Kwon Lee, Joonwon Lee, Seung Ryoul Maeng:
Adopting system call based address translation into user-level communication.
26-29
- Jung Ho Ahn, William J. Dally:
Data parallel address architecture.
30-33
- Noel Eisley, Li-Shiuan Peh, Li Shang:
In-network cache coherence.
34-37
- Ram Srinivasan, Jeanine Cook, Olaf M. Lubeck:
Performance modeling using Monte Carlo simulation.
38-41
Volume 5,
Number 2,
July-December 2006
- Jean-Luc Gaudiot, Yale N. Patt, Kevin Skadron:
Foreword.
- Oguz Ergin, Osman S. Unsal, Xavier Vera, Antonio González:
Exploiting Narrow Values for Soft Error Tolerance.
- Wentong Li, Saraju P. Mohanty, Krishna M. Kavi:
A Page-based Hybrid (Software-Hardware) Dynamic Memory Allocator.
- James Donald, Margaret Martonosi:
An Efficient, Practical Parallelization Methodology for Multicore Architecture Simulation.
- Anne Bracy, Kshitij Doshi, Quinn Jacobson:
Disintermediated Active Communication.
- Arindam Mallik, Bin Lin, Gokhan Memik, Peter A. Dinda, Robert P. Dick:
User-Driven Frequency Scaling.
- Milo M. K. Martin, Colin Blundell, E. Lewis:
Subtleties of Transactional Memory Atomicity Semantics.
- Graham D. Price, Manish Vachharajani:
A Case for Compressing Traces with BDDs.
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