IEEE Computer Architecture Letters, Volume 10
Volume 10, Number 1, January 2011
Kevin Skadron: Editorial: Letter from the Editor-in-Chief. 1-3- Jie Tang, Shaoshan Liu, Zhimin Gu, Chen Liu, Jean-Luc Gaudiot: Prefetching in Embedded Mobile Systems Can Be Energy-Efficient. 8-11
- Omer Khan, Mieszko Lis, Yildiz Sinangil, Srinivas Devadas: DCC: A Dependable Cache Coherence Multicore Architecture. 12-15
- Paul Rosenfeld, Elliott Cooper-Balis, Bruce Jacob: DRAMSim2: A Cycle Accurate Memory System Simulator. 16-19
- Xiaoqun Wang, Zhen Ji, Chen Fu, Ming Hu: GCMS: A Global Contention Management Scheme in Hardware Transactional Memory. 24-27
Volume 10, Number 2, 2011
- Jason Mars, Lingjia Tang, Robert Hundt: Heterogeneity in "Homogeneous" Warehouse-Scale Computers: A Performance Opportunity. 29-32
- George Michelogiannakis, Nan Jiang, Daniel U. Becker, William J. Dally: Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks. 33-36
- Chen-Han Ho, Garret Staus, Aaron Ullmer, Karu Sakaralingam: Exploring the Interaction Between Device Lifetime Reliability and Security Vulnerabilities. 37-40
- Carles Hernández, Antoni Roca, Jose Flich, Federico Silla, José Duato: Fault-Tolerant Vertical Link Design for Effective 3D Stacking. 41-44
- Inseok Choi, Minshu Zhao, Xu Yang, Donald Yeung: Experience with Improving Distributed Shared Cache Performance on Tilera's Tile Processor. 45-48
- Pablo Prieto, Valentin Puente, José-Ángel Gregorio: Multilevel Cache Modeling for Chip-Multiprocessor Systems. 49-52
- Kostas Siozios, Dimitrios Rodopoulos, Dimitrios Soudris: On Supporting Rapid Thermal Analysis. 53-56
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last updated on 2013-06-18T214307 by the dblp team