 | 2011 |
|---|
| 40 |       | Hans Vandierendonck,
George Tzenakis,
Dimitrios S. Nikolopoulos:
A Unified Scheduler for Recursive and Task Dataflow Parallelism.
PACT 2011: 1-11 |
| 39 | | Hans Vandierendonck,
André Seznec:
Fairness Metrics for Multi-Threaded Processors.
Computer Architecture Letters 10(1): 4-7 (2011) |
| 38 | | Hans Vandierendonck,
Tom Mens:
Averting the Next Software Crisis.
IEEE Computer 44(4): 88-90 (2011) |
| 37 | | Hans Vandierendonck,
André Seznec:
Managing SMT resource usage through speculative instruction window weighting.
TACO 8(3): 12 (2011) |
| 2010 |
|---|
| 36 | | Bertrand Rousseau,
Philippe Manet,
Igor Loiselle,
Jean-Didier Legat,
Hans Vandierendonck:
A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms.
DASIP 2010: 273-280 |
| 35 | | Hans Vandierendonck,
Koen De Bosschere:
Implicit hints: Embedding hint bits in programs without ISA changes.
ICCD 2010: 364-369 |
| 34 | | Hans Vandierendonck,
Sean Rul,
Koen De Bosschere:
The Paralax infrastructure: automatic parallelization with a helping hand.
PACT 2010: 389-400 |
| 33 | | Hans Vandierendonck,
Sean Rul,
Koen De Bosschere:
Accelerating Multiple Sequence Alignment with the Cell BE Processor.
Comput. J. 53(6): 814-826 (2010) |
| 32 | | Sean Rul,
Hans Vandierendonck,
Koen De Bosschere:
A profile-based tool for finding pipeline parallelism in sequential programs.
Parallel Computing 36(9): 531-551 (2010) |
| 2009 |
|---|
| 31 | | Sean Rul,
Hans Vandierendonck,
Koen De Bosschere:
Towards automatic program partitioning.
Conf. Computing Frontiers 2009: 89-98 |
| 30 | | Hans Vandierendonck,
André Seznec:
Fetch Gating Control through Speculative Instruction Window Weighting.
T. HiPEAC 2: 128-148 (2009) |
| 2008 |
|---|
| 29 | | Hans Vandierendonck,
Koen De Bosschere:
Constructing Optimal XOR-Functions to Minimize Cache Conflict Misses.
ARCS 2008: 261-272 |
| 28 | | Hans Vandierendonck,
Sean Rul,
Michiel Questier,
Koen De Bosschere:
Experiences with Parallelizing a Bio-informatics Program on the Cell BE.
HiPEAC 2008: 161-175 |
| 27 | | Sean Rul,
Hans Vandierendonck,
Koen De Bosschere:
Extracting coarse-grain parallelism in general-purpose programs.
PPOPP 2008: 281-282 |
| 26 | | Hans Vandierendonck,
Veerle Desmet,
Koen De Bosschere:
Behavior-Based Branch Prediction by Dynamically Clustering Branch Instructions.
J. Inf. Sci. Eng. 24(3): 919-931 (2008) |
| 25 | | Hans Vandierendonck,
André Seznec:
Speculative return address stack management revisited.
TACO 5(3): (2008) |
| 2007 |
|---|
| 24 | | Hans Vandierendonck,
Philippe Manet,
Thibault Delavallee,
Igor Loiselle,
Jean-Didier Legat:
By-passing the out-of-order execution pipeline to increase energy-efficiency.
Conf. Computing Frontiers 2007: 97-104 |
| 23 | | Hans Vandierendonck,
André Seznec:
Fetch Gating Control Through Speculative Instruction Window Weighting.
HiPEAC 2007: 120-135 |
| 22 | | Veerle Desmet,
Hans Vandierendonck,
Koen De Bosschere:
Clustered indexing for branch predictors.
Microprocessors and Microsystems 31(3): 168-177 (2007) |
| 21 | | Sean Rul,
Hans Vandierendonck,
Koen De Bosschere:
Function level parallelism driven by data dependencies.
SIGARCH Computer Architecture News 35(1): 55-62 (2007) |
| 2006 |
|---|
| 20 | | Hans Vandierendonck,
Philippe Manet,
Jean-Didier Legat:
Application-specific reconfigurable XOR-indexing to eliminate cache conflict misses.
DATE 2006: 357-362 |
| 19 | | Joshua J. Yi,
Hans Vandierendonck,
Lieven Eeckhout,
David J. Lilja:
The exigency of benchmark and compiler drift: designing tomorrow's processors with yesterday's tools.
ICS 2006: 75-86 |
| 18 | | Hans Vandierendonck,
Pedro Trancoso:
Building and Validating a Reduced TPC-H Benchmark.
MASCOTS 2006: 383-392 |
| 17 | | Hans Vandierendonck,
Koen De Bosschere:
On the Impact of OS and Linker Effects on Level-2 Cache Performance.
MASCOTS 2006: 87-95 |
| 2005 |
|---|
| 16 | | Pedro Trancoso,
Christodoulos Adamou,
Hans Vandierendonck:
Reducing TPC-H Benchmarking Time.
Panhellenic Conference on Informatics 2005: 641-650 |
| 15 | | Hans Vandierendonck,
Koenraad De Bosschere:
XOR-Based Hash Functions.
IEEE Trans. Computers 54(7): 800-812 (2005) |
| 2004 |
|---|
| 14 | | Hans Vandierendonck,
Koen De Bosschere:
Eccentric and fragile benchmarks.
ISPASS 2004: 2-11 |
| 13 | | Hans Vandierendonck,
Koen De Bosschere:
On Generating Set Index Functions for Randomized Caches.
Comput. J. 47(2): 245-258 (2004) |
| 2003 |
|---|
| 12 | | Hans Vandierendonck,
Hans Logie,
Koenraad De Bosschere:
Trace Substitution.
Euro-Par 2003: 556-565 |
| 11 | | Bjorn De Sutter,
Hans Vandierendonck,
Bruno De Bus,
Koenraad De Bosschere:
On the side-effects of code abstraction.
LCTES 2003: 244-253 |
| 10 |  | Hans Vandierendonck,
Koenraad De Bosschere:
Trade-offs for Skewed-Associative Caches.
PARCO 2003: 465-474 |
| 9 | | Lieven Eeckhout,
Hans Vandierendonck,
Koenraad De Bosschere:
Designing Computer Architecture Research Workloads.
IEEE Computer 36(2): 65-71 (2003) |
| 8 | | Lieven Eeckhout,
Hans Vandierendonck,
Koenraad De Bosschere:
Quantifying the Impact of Input Data Sets on Program Behavior and its Applications.
J. Instruction-Level Parallelism 5: (2003) |
| 7 | | Hans Vandierendonck,
Koen De Bosschere:
Highly accurate and efficient evaluation of randomising set index functions.
Journal of Systems Architecture 48(13-15): 429-452 (2003) |
| 2002 |
|---|
| 6 | | Hans Vandierendonck,
Alex Ramírez,
Koenraad De Bosschere,
Mateo Valero:
A Comparative Study of Redundancy in Trace Caches (Research Note).
Euro-Par 2002: 512-516 |
| 5 | | Lieven Eeckhout,
Hans Vandierendonck,
Koenraad De Bosschere:
Workload Design: Selecting Representative Program-Input Pairs.
IEEE PACT 2002: 83-94 |
| 4 | | Hans Vandierendonck,
Koenraad De Bosschere:
An Address Transformation Combining Block- and Word-Interleaving.
Computer Architecture Letters 1: (2002) |
| 2001 |
|---|
| 3 | | Bart Goeman,
Hans Vandierendonck,
Koenraad De Bosschere:
Differential FCM: Increasing Value Prediction Accuracy by Improving Table Usage Efficiency.
HPCA 2001: 207-216 |
| 2000 |
|---|
| 2 | | Henk Neefs,
Hans Vandierendonck,
Koenraad De Bosschere:
A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks.
HPCA 2000: 313-324 |
| 1 | | Hans Vandierendonck,
Koenraad De Bosschere:
A Comparison of Locality-Based and Recency-Based Replacement Policies.
ISHPC 2000: 310-318 |
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