Dipankar Sarkar

	2011
18		Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chitta Mandal: Equivalence Checking of Array-Intensive Programs. ISVLSI 2011: 156-161
17		Chandan Karfa, Chitta Mandal, Dipankar Sarkar: Verification of Register Transfer Level Low Power Transformations. ISVLSI 2011: 313-314
	2010
16		Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal: Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques. ISVLSI 2010: 428-433
15		Santosh Biswas, Dipankar Sarkar, Siddhartha Mukhopadhyay, Amit Patra: Fairness of Transitions in Diagnosability of Discrete Event Systems. Discrete Event Dynamic Systems 20(3): 349-376 (2010)
14		Chandan Karfa, Dipankar Sarkar, Chitta Mandal: Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 479-492 (2010)
13		Soumyajit Dey, Dipankar Sarkar, Anupam Basu: A Tag Machine Based Performance Evaluation Method for Job-Shop Schedules. IEEE Trans. on CAD of Integrated Circuits and Systems 29(7): 1028-1041 (2010)
12		Santosh Biswas, Dipankar Sarkar, Siddhartha Mukhopadhyay: Diagnosability of delay-deadline failures in fair real time discrete event models. Int. J. Systems Science 41(7): 763-782 (2010)
	2008
11		Chandan Karfa, Dipankar Sarkar, Chitta Mandal, P. Kumar: An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 556-569 (2008)
10		Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra, Dipankar Sarkar: Unified Technique for on-Line Testing of Digital Circuits: Delay and Stuck-at Fault Models. Journal of Circuits, Systems, and Computers 17(6): 1069-1089 (2008)
	2007
9		Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade: Hand-in-hand verification of high-level synthesis. ACM Great Lakes Symposium on VLSI 2007: 429-434
8		Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, Chris Reade: Register Sharing Verification During Data-Path Synthesis. ICCTA 2007: 135-140
7		Prodip Bhowal, Dipankar Sarkar, Siddhartha Mukhopadhyay, Anupam Basu: Fault diagnosis in discrete time hybrid systems - A case study. Inf. Sci. 177(5): 1290-1308 (2007)
	2006
6		Santosh Biswas, Siddhartha Mukhopadhyay, P. Patra, Dipankar Sarkar: Concurrent Testing of Digital Circuits for Advanced Fault Models. DDECS 2006: 204-209
5		Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade: A Formal Verification Method of Scheduling in High-level Synthesis. ISQED 2006: 71-78
4		Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade: Verification of Scheduling in High-level Synthesis. ISVLSI 2006: 141-146
	2005
3		Santosh Biswas, P. Srikanth, R. Jha, Siddhartha Mukhopadhyay, Amit Patra, Dipankar Sarkar: On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models. Asian Test Symposium 2005: 88-93
	2004
2		Batsayan Das, Dipankar Sarkar, Santanu Chattopadhyay: Model checking on state transition diagram. ASP-DAC 2004: 412-417
	2000
1		Dipankar Sarkar: Status Condition Analysis during Data Path Verification of Sequential Circuits. VLSI Design 2000: 70-75

Coauthor Index

1	Kunal Banerjee	[18]
2	Anupam Basu	[7] [13]
3	Prodip Bhowal	[7]
4	Santosh Biswas	[3] [6] [10] [12] [15]
5	Santanu Chattopadhyay	[2]
6	Batsayan Das	[2]
7	Soumyajit Dey	[13]
8	R. Jha	[3]
9	Chandan Karfa	[4] [5] [8] [9] [11] [14] [16] [17] [18]
10	P. Kumar	[11]
11	Chittaranjan A. Mandal (Chitta Mandal)	[4] [5] [8] [9] [11] [14] [16] [17] [18]
12	Siddhartha Mukhopadhyay	[3] [6] [7] [10] [12] [15]
13	Amit Patra	[3] [10] [15]
14	P. Patra	[6]
15	S. R. Pentakota	[4] [5]
16	Chris Reade	[4] [5] [8] [9]
17	P. Srikanth	[3]

Colors in the list of coauthors

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