Jean Michel Portal

	2012
41		Jean Michel Portal, Marc Bocquet, Damien Deleruyelle, Christophe Muller: Non-Volatile Flip-Flop Based on Unipolar ReRAM for Power-Down Applications. J. Low Power Electronics 8(1): 1-10 (2012)
	2011
40		Ch. Muller, Damien Deleruyelle, Olivier Ginez, Jean Michel Portal, Marc Bocquet: Design challenges for prototypical and emerging memory concepts relying on resistance switching. CICC 2011: 1-7
39		A. Marzaki, V. Bidal, R. Laffont, Wenceslas Rahajandraibe, Jean Michel Portal, Rachid Bouchakour: PSP based DCG-FGT transistor model including characterization procedure. ICECS 2011: 228-231
38		Y. Joly, L. Truphemus, L. Lopez, Jean Michel Portal, Hassen Aziza, F. Julien, Pascal Fornara: Temperature and hump effect impact on output voltage spread of low power bandgap designed in the sub-threshold area. ISCAS 2011: 2549-2552
37		Fabrice Rigaud, Jean Michel Portal, Hassen Aziza, Didier Née, Julien Vast, Fabrice Argoud, Bertrand Borot: Back-end soft and hard defect monitoring using a single test chip. Microelectronics Reliability 51(6): 1136-1141 (2011)
36		Y. Joly, L. Lopez, Jean Michel Portal, Hassen Aziza, Jean-Luc Ogier, Y. Bert, F. Julien, Pascal Fornara: Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress. Microelectronics Reliability 51(9-11): 1561-1563 (2011)
	2009
35		Olivier Ginez, Jean Michel Portal, Hassen Aziza: An on-line testing scheme for repairing purposes in Flash memories. DDECS 2009: 120-123
34		Olivier Ginez, Jean Michel Portal, Ch. Muller: Design and Test Challenges in Resistive Switching RAM (ReRAM): An Electrical Model for Defect Injections. European Test Symposium 2009: 61-66
33		Laurent Remy, Philippe Coll, Fabrice Picot, Philippe Mico, Jean Michel Portal: Definition of an innovative filling structure for digital blocks : the DFM filler cell. ICECS 2009: 73-76
	2008
32		Manuel Sellier, Jean Michel Portal, Bertrand Borot, Steve Colquhoun, Richard Ferrant, Frédéric Boeuf, Alexis Farcy: Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework. ISQED 2008: 492-497
31		Olivier Ginez, Jean Michel Portal, Hassen Aziza: A High-Speed Structural Method for Testing Address Decoder Faults in Flash Memories. ITC 2008: 1-10
30		Laurent Remy, Philippe Coll, Fabrice Picot, Philippe Mico, Jean Michel Portal: Metal filling impact on standard cells: definition of the metal fill corner concept. SBCCI 2008: 16-21
29		Hassen Aziza, Emmanuel Bergeret, Jean Michel Portal, Olivier Ginez: A Novel Low Power Oriented Design Methodology for Analog Blocks. J. Low Power Electronics 4(1): 60-67 (2008)
	2007
28		Laurent Lopez, Jean Michel Portal, Didier Née: A New Embedded Measurement Structure for eDRAM Capacitor CoRR abs/0710.4736: (2007)
	2006
27		B. Saillet, A. Regnier, Jean Michel Portal, B. Delsuc, R. Laffont, Pascal Masson, Rachid Bouchakour: MM11 based flash memory cell model including characterization procedure. ISCAS 2006
	2005
26		Laurent Lopez, Jean Michel Portal, Didier Née: A New Embedded Measurement Structure for eDRAM Capacitor. DATE 2005: 462-463
25		B. Saillet, Jean Michel Portal, Didier Née: Flash Memory Cell: Parametric Test Data Reconstruction for Process Monitoring. DFT 2005: 131-139
24		Jean Michel Portal, Hassen Aziza, Didier Née: EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement. J. Electronic Testing 21(1): 33-42 (2005)
	2004
23		S. Bernardini, Jean Michel Portal, Pascal Masson: A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology. DATE 2004: 1404-1405
22		Anna Labbé, Annie Pérez, Jean Michel Portal: Efficient hardware implementation of a CRYPTO-MEMORY based on AES algorithm and SRAM architecture. ISCAS (2) 2004: 637-640
	2003
21		L. Forli, Jean Michel Portal, Didier Née, Bertrand Borot: Infrastructure IP for Back-End Yield Improvement. ITC 2003: 1129-1134
20		Jean Michel Portal, Hassen Aziza, Didier Née: EEPROM Memory: Threshold Voltage Built In Self Diagnosis. ITC 2003: 23-28
	2002
19		Jean Michel Portal, L. Forli, Didier Née: Floating-gate EEPROM cell: threshold voltage sensibility to geometry. ISCAS (1) 2002: 557-560
18		Jean Michel Portal, L. Forli, Didier Née: Floating-gate EEPROM cell model based on MOS model 9. ISCAS (3) 2002: 799-802
17		Jean Michel Portal, L. Forli, Hassen Aziza, Didier Née: An Automated Methodology to Diagnose Geometric Defect in the EEPROM Cell. ITC 2002: 31-36
16		Jean Michel Portal, L. Forli, Hassen Aziza, Didier Née: An Automated Design Methodology for EEPROM Cell (ADE). MTDT 2002: 137-142
	2001
15		Michel Renovell, Penelope Faure, Jean Michel Portal, Joan Figueras, Yervant Zorian: IS-FPGA : a new symmetric FPGA architecture with implicit scan. ITC 2001: 924-931
14		Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian: A Discussion on Test Pattern Generation for FPGA - Implemented Circuits. J. Electronic Testing 17(3-4): 283-290 (2001)
	2000
13		Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian: TOF: a tool for test pattern generation optimization of an FPGA application oriented test. Asian Test Symposium 2000: 323-328
12		Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. J. Electronic Testing 16(3): 289-299 (2000)
11		Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Testing the Local Interconnect Resources of SRAM-Based FPGA's. J. Electronic Testing 16(5): 513-520 (2000)
	1999
10		Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Minimizing the Number of Test Configurations for Different FPGA Families. Asian Test Symposium 1999: 363-368
9		Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. DATE 1999: 618-622
8		Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-Based FPGAs: Testing the Embedded RAM Modules. J. Electronic Testing 14(1-2): 159-167 (1999)
	1998
7		Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. Asian Test Symposium 1998: 266-271
6		Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: RAM-Based FPGA's: A Test Approach for the Configurable Logic. DATE 1998: 82-88
5		Cecilia Metra, Michel Renovell, G. Mojoli, Jean Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi: Novel Technique for Testing FPGAs. DATE 1998: 89-94
4		Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. FPL 1998: 139-148
3		Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-based FPGA's: testing the LUT/RAM modules. ITC 1998: 1102-1111
2		Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Testing the Interconnect of RAM-Based FPGAs. IEEE Design & Test of Computers 15(1): 45-50 (1998)
	1997
1		Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. Asian Test Symposium 1997: 254-

Coauthor Index

1	Fabrice Argoud	[37]
2	Hassen Aziza	[16] [17] [20] [24] [29] [31] [35] [36] [37] [38]
3	Emmanuel Bergeret	[29]
4	S. Bernardini	[23]
5	Y. Bert	[36]
6	V. Bidal	[39]
7	Marc Bocquet	[40] [41]
8	Frédéric Boeuf	[32]
9	Bertrand Borot	[21] [32] [37]
10	Rachid Bouchakour	[27] [39]
11	Philippe Coll	[30] [33]
12	Steve Colquhoun	[32]
13	Damien Deleruyelle	[40] [41]
14	B. Delsuc	[27]
15	Alexis Farcy	[32]
16	Penelope Faure	[13] [14] [15]
17	Richard Ferrant	[32]
18	Joan Figueras	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
19	L. Forli	[16] [17] [18] [19] [21]
20	Pascal Fornara	[36] [38]
21	Olivier Ginez	[29] [31] [34] [35] [40]
22	Y. Joly	[36] [38]
23	F. Julien	[36] [38]
24	Anna Labbé	[22]
25	R. Laffont	[27] [39]
26	L. Lopez	[36] [38]
27	Laurent Lopez	[26] [28]
28	A. Marzaki	[39]
29	Pascal Masson	[23] [27]
30	Cecilia Metra	[5]
31	Philippe Mico	[30] [33]
32	G. Mojoli	[5]
33	Ch. Muller	[34] [40]
34	Christophe Muller	[41]
35	Didier Née	[16] [17] [18] [19] [20] [21] [24] [25] [26] [28] [37]
36	Jean-Luc Ogier	[36]
37	Sandro Pastore	[5]
38	Annie Pérez	[22]
39	Fabrice Picot	[30] [33]
40	Wenceslas Rahajandraibe	[39]
41	A. Regnier	[27]
42	Laurent Remy	[30] [33]
43	Michel Renovell	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
44	Fabrice Rigaud	[37]
45	B. Saillet	[25] [27]
46	Davide Salvi	[5]
47	Giacomo R. Sechi	[5]
48	Manuel Sellier	[32]
49	L. Truphemus	[38]
50	Julien Vast	[37]
51	Yervant Zorian	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]

Colors in the list of coauthors

Last update Sat Feb 11 22:55:45 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page