 | 1998 |
| 23 |  | Luc De Coster,
Marleen Adé,
Rudy Lauwereins,
J. A. Peperstraete:
Code Generation for Compiled Bit-True Simulation of DSP Applications.
ISSS 1998: 9-14 |
| 22 |  | Luc De Coster,
Rudy Lauwereins,
J. A. Peperstraete:
Rapid prototyping of an adaptive noise canceler using GRAPE.
Signal Processing 64(1): 61-70 (1998) |
| 1997 |
| 21 |  | Marleen Adé,
Rudy Lauwereins,
J. A. Peperstraete:
Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets.
DAC 1997: 64-69 |
| 1996 |
| 20 |  | Luc De Coster,
Marc Engels,
Rudy Lauwereins,
J. A. Peperstraete:
Global Approach for Compiled Bit-True Simulation of DSP Systems.
Euro-Par, Vol. II 1996: 236-239 |
| 19 |  | P. Wauters,
Marc Engels,
Rudy Lauwereins,
J. A. Peperstraete:
Cyclo-Dynamic Dataflow.
PDP 1996: 319-326 |
| 18 |  | Greet Bilsen,
Marc Engels,
Rudy Lauwereins,
J. A. Peperstraete:
Cycle-static dataflow.
IEEE Transactions on Signal Processing 44(2): 397-408 (1996) |
| 1995 |
| 17 |  | Greet Bilsen,
Rudy Lauwereins,
J. A. Peperstraete:
Compile-time scheduling with resource-constraints.
HICSS (2) 1995: 153-162 |
| 16 |  | Johan Vounckx,
Geert Deconinck,
Rudy Lauwereins,
J. A. Peperstraete:
A Loader for Injured Massively Parallel Regular Networks.
Parallel and Distributed Computing and Systems 1995: 178-180 |
| 15 |  | J. A. Peperstraete,
R. Cuyvers,
Rudy Lauwereins:
A User-Adaptable Fault Tolerant Motor Controller using an Argument Flow Multiprocessor System.
Parallel and Distributed Computing and Systems 1995: 317-320 |
| 14 |  | Geert Deconinck,
Johan Vounckx,
Rudy Lauwereins,
J. A. Peperstraete:
A User-triggered Checkpointing Library for Computationintensive Applications.
Parallel and Distributed Computing and Systems 1995: 321-324 |
| 13 |  | Rudy Lauwereins,
Marc Engels,
Marleen Adé,
J. A. Peperstraete:
Grape-II: A System-Level Prototyping Environment for DSP Applications.
IEEE Computer 28(2): 35-43 (1995) |
| 1994 |
| 12 |  | Manga J. P. Bekambo,
J. A. Peperstraete:
Control of a Dead-time Process by a Fuzzy Algorithm.
Applied Informatics 1994: 143-145 |
| 11 |  | Valeriu Beiu,
J. A. Peperstraete,
Joos Vandewalle,
Rudy Lauwereins:
VLSI complexity reduction by piece-wise approximation of the sigmoid function.
ESANN 1994 |
| 10 |  | Chris Caerts,
Rudy Lauwereins,
J. A. Peperstraete:
PDG: A Portable Process-Level Debugger for CSP-Style Parallel Programs.
HICSS (2) 1994: 634-643 |
| 9 |  | Johan Vounckx,
Geert Deconinck,
Rudy Lauwereins,
J. A. Peperstraete:
Fault-Tolerant Compact Routing Based on Reduced Structural Information in Wormhole-Switching Based Networks.
SIROCCO 1994: 125-148 |
| 8 |  | Valeriu Beiu,
J. A. Peperstraete,
Joos Vandewalle,
Rudy Lauwereins:
Closse Approximations of Sigmoid Functions by Sum of Step for VLSI Implementation of Neural Networks.
Sci. Ann. Cuza Univ. 3: 5-34 (1994) |
| 1993 |
| 7 |  | Valeriu Beiu,
J. A. Peperstraete,
Joos Vandewalle,
Rudy Lauwereins:
Efficient decomposition of comparison and its applications.
ESANN 1993 |
| 6 |  | Marc Engels,
Rudy Lauwereins,
J. A. Peperstraete,
Arthur H. M. van Roermund:
Design of a processing board for a programmable multi-VSP system.
VLSI Signal Processing 5(2-3): 171-184 (1993) |
| 1991 |
| 5 |  | Chris Caerts,
Rudy Lauwereins,
J. A. Peperstraete:
A Powerful Hig-Level Debugger for Parallel Programs.
ACPC 1991: 54-64 |
| 4 |  | Marc Engels,
Rudy Lauwereins,
J. A. Peperstraete:
Rapid Prototyping for DSP Systems with Multiprocessors.
IEEE Design & Test of Computers 8(2): 52-62 (1991) |
| 1987 |
| 3 |  | Rudy Lauwereins,
J. A. Peperstraete:
An Integrated Software-Hardware Multiprocesor Project.
ICPP 1987: 618-620 |
| 1983 |
| 2 |  | L. J. Caluwaerts,
J. Debacker,
J. A. Peperstraete:
Implementing Streams on a Data Flow Computer System With Paged Memory
ISCA 1983: 76-83 |
| 1982 |
| 1 |  | L. J. Caluwaerts,
J. Debacker,
J. A. Peperstraete:
A data flow architecture with a paged memory system.
ISCA 1982: 120-127 |