Alberto Palacios Pawlovsky

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2005

1 Alberto Palacios Pawlovsky: Using simulated annealing to generate input pairs to measure the maximum power dissipation in combinational CMOS circuits. IEICE Electronic Express 2(4): 115-120 (2005)

	2005
1		Alberto Palacios Pawlovsky: Using simulated annealing to generate input pairs to measure the maximum power dissipation in combinational CMOS circuits. IEICE Electronic Express 2(4): 115-120 (2005)

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