 | 2010 |
|---|
| 8 |       | Parag K. Lala,
Adam Mathews,
James Patrick Parkerson:
An Approach for Implementing State Machines with Online Testability.
VLSI Design 2010: (2010) |
| 2006 |
|---|
| 7 | | Dilip P. Vasudevan,
Parag K. Lala,
Jia Di,
James Patrick Parkerson:
Reversible-logic design with online testability.
IEEE T. Instrumentation and Measurement 55(2): 406-414 (2006) |
| 6 | | Parag K. Lala,
B. Kiran Kumar,
James Patrick Parkerson:
On self-healing digital system design.
Microelectronics Journal 37(4): 353-362 (2006) |
| 2005 |
|---|
| 5 | | C. K. Tang,
Parag K. Lala,
James Patrick Parkerson:
A Technique for Designing Totally Self-Checking Domino Logic Circuits.
ISQED 2005: 128-132 |
| 4 | | Dilip P. Vasudevan,
Parag K. Lala,
James Patrick Parkerson:
CMOS Realization of Online Testable Reversible Logic Gates.
ISVLSI 2005: 309-310 |
| 2004 |
|---|
| 3 | | Dilip P. Vasudevan,
Parag K. Lala,
James Patrick Parkerson:
A Novel Approach for On-line Testable Reversible Logic Circuit Desig.
Asian Test Symposium 2004: 325-330 |
| 2 |  | Dilip P. Vasudevan,
James Patrick Parkerson,
Parag K. Lala:
Logic implementation using a reversible gate.
Circuits, Signals, and Systems 2004: 452-456 |
| 1 | | Dilip P. Vasudevan,
Parag K. Lala,
James Patrick Parkerson:
Online Testable Reversible Logic Circuit Design using NAND Blocks.
DFT 2004: 324-331 |
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