Joonbae Park

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1999

1 Joonbae Park, Yido Koo, Wonchan Kim: A Semi-Digital Delay Locked Loop for Clock Skew Minimization. VLSI Design 1999: 584-588

	1999
1		Joonbae Park, Yido Koo, Wonchan Kim: A Semi-Digital Delay Locked Loop for Clock Skew Minimization. VLSI Design 1999: 584-588

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