Ajit Pal

	2011
28		Sukanta Bhattacharya, Tanmay De, Ajit Pal: An Algorithm for Traffic Grooming in WDM Mesh Networks Using Dynamic Path Selection Strategy. ICDCN 2011: 263-268
27		Mallikarjuna Rao Nimmagadda, Ajit Pal: Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design. ISVLSI 2011: 345-346
	2010
26		Aritra Hazra, Srobona Mitra, Pallab Dasgupta, Ajit Pal, Debabrata Bagchi, Kaustav Guha: Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent. DAC 2010: 773-776
25		Suman Paul, Subrata Nandi, Ajit Pal: Credit Reputation Propagation: A Strategy to Curb Free-Riding in a Large BitTorrent Swarm. ICDCN 2010: 207-218
24		Sukanta Bhattacharya, Tanmay De, Ajit Pal: Traffic grooming in WDM mesh networks using dynamic path selection strategy. WOCN 2010: 1-5
23		Sudip Roy, Ajit Pal: A New Technique for Runtime Leakage Reduction and Its Sensitivity and Parametric Yield Analysis Under Effective Channel-Length Variation. J. Low Power Electronics 6(1): 80-92 (2010)
	2009
22		Ajit Pal, Santanu Chattopadhyay: Synthesis & Testing for Low Power. VLSI Design 2009: 37-38
	2008
21		Sudip Roy, Ajit Pal: Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations? DSD 2008: 282-289
20		Tanmay De, Ajit Pal, Indranil Sengupta: Routing and Wavelength Assignment in All Optical Networks Based on Clique Partitioning. ICDCN 2008: 452-463
19		Tanmay De, Puneet Jain, Ajit Pal, Indranil Sengupta: A genetic algorithm based approach for traffic grooming, routing and wavelength assignment in optical WDM mesh networks. ICON 2008: 1-6
18		Sujan Kundu, Sudip Roy, Ajit Pal: A power-aware wireless sensor network based bridge monitoring system. ICON 2008: 1-7
	2007
17		Akepati Sravan, Sujan Kundu, Ajit Pal: Low Power Sensor Node for a Wireless Sensor Network. VLSI Design 2007: 445-450
	2006
16		Gopal Paul, Ajit Pal, Bhargab B. Bhattacharya: On finding the minimum test set of a BDD-based circuit. ACM Great Lakes Symposium on VLSI 2006: 169-172
15		Gopal Paul, S. N. Pradhan, Ajit Pal, Bhargab B. Bhattacharya: Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic. APCCAS 2006: 1504-1507
	2005
14		Ajit Pal, Ajay D. Kshemkalyani, Rajeev Kumar, Arobinda Gupta: Distributed Computing - IWDC 2005, 7th International Workshop, Kharagpur, India, December 27-30, 2005, Proceedings Springer 2005
	2004
13		Ajit Pal, Umesh Patel: Routing and Wavelength Assignment in Wavelength Division Multiplexing Networks. IWDC 2004: 391-396
12		Maitrali Marik, Ajit Pal: Energy-aware Logic Synthesis and Technology Mapping for MUX-based FPGAs. VLSI Design 2004: 73-78
11		Debasis Samanta, Ajit Pal: Synthesis of Low Power High Performance Dual-VT PTL Circuits. VLSI Design 2004: 85-
	2003
10		Debasis Samanta, Ajit Pal: Synthesis of Dual-VT Dynamic CMOS Circuits. VLSI Design 2003: 303-308
	2002
9		Debasis Samanta, Ajit Pal: Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits. VLSI Design 2002: 193-198
8		Debasis Samanta, Nishant Sinha, Ajit Pal: Synthesis of High Performance Low Power Dynamic CMOS Circuits. VLSI Design 2002: 99-104
	2001
7		Nikhil Tripathi, Amit M. Bhosle, Debasis Samanta, Ajit Pal: Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits. VLSI Design 2001: 227-
	1998
6		Rajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal: An algorithm for finding a non-trivial lower bound for channel routing1. Integration 25(1): 71-84 (1998)
	1997
5		Rajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal: An Algorithm for Finding a Non-Trivial Lower Bound for Channel Routing. VLSI Design 1997: 531-533
	1995
4		Rajat K. Pal, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal: Computing area and wire length efficient routes for channels. VLSI Design 1995: 196-201
3		Rajat K. Pal, A. K. Datta, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal: A general graph theoretic framework for multi-layer channel routing. VLSI Design 1995: 202-207
	1993
2		Rajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal, Alak K. Dutta: NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient Heuristic. VLSI Design 1993: 80-83
	1986
1		Ajit Pal: An Algorithm for Optimal Logic Design Using Multiplexers. IEEE Trans. Computers 35(8): 755-757 (1986)

Coauthor Index

1	Debabrata Bagchi	[26]
2	Bhargab B. Bhattacharya	[15] [16]
3	Sukanta Bhattacharya	[24] [28]
4	Amit M. Bhosle	[7]
5	Santanu Chattopadhyay	[22]
6	M. M. Das	[3] [4]
7	Pallab Dasgupta	[26]
8	A. K. Datta	[3]
9	Tanmay De	[19] [20] [24] [28]
10	Alak K. Dutta	[2]
11	Kaustav Guha	[26]
12	Arobinda Gupta	[14]
13	Aritra Hazra	[26]
14	Puneet Jain	[19]
15	Ajay D. Kshemkalyani	[14]
16	Rajeev Kumar	[14]
17	Sujan Kundu	[17] [18]
18	Maitrali Marik	[12]
19	Srobona Mitra	[26]
20	Subrata Nandi	[25]
21	Mallikarjuna Rao Nimmagadda	[27]
22	Rajat K. Pal	[2] [3] [4] [5] [6]
23	Sudebkumar Prasant Pal	[2] [3] [4] [5] [6]
24	Umesh Patel	[13]
25	Gopal Paul	[15] [16]
26	Suman Paul	[25]
27	S. N. Pradhan	[15]
28	Sudip Roy	[18] [21] [23]
29	Debasis Samanta	[7] [8] [9] [10] [11]
30	Indranil Sengupta	[19] [20]
31	Nishant Sinha	[8]
32	Akepati Sravan	[17]
33	Nikhil Tripathi	[7]

Colors in the list of coauthors

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