Seungwhun Paik

	2012
19		Insup Shin, Seungwhun Paik, Dongwan Shin, Youngsoo Shin: HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures. IEEE Trans. VLSI Syst. 20(4): 593-604 (2012)
	2011
18		Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin: Pulser gating: A clock gating of pulsed-latch circuits. ASP-DAC 2011: 190-195
17		Donkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin: Selectively patterned masks: Structured ASIC with asymptotically ASIC performance. ASP-DAC 2011: 376-381
16		Seungwhun Paik, Gi-Joon Nam, Youngsoo Shin: Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power. ICCAD 2011: 640-646
15		Youngsoo Shin, Seungwhun Paik: Pulsed-Latch Circuits: A New Dimension in ASIC Design. IEEE Design & Test of Computers 28(6): 50-57 (2011)
14		Seungwhun Paik, Seonggwan Lee, Youngsoo Shin: Retiming Pulsed-Latch Circuits With Regulating Pulse Width. IEEE Trans. on CAD of Integrated Circuits and Systems 30(8): 1114-1127 (2011)
13		Lee-eun Yu, Changsik Shin, Seungwhun Paik, Jing-Jia Liou, Youngsoo Shin: Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks. Journal of Circuits, Systems, and Computers 20(8): 1547-1569 (2011)
	2010
12		Jun Seomun, Seungwhun Paik, Youngsoo Shin: Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design. ASP-DAC 2010: 581-586
11		Seungwhun Paik, Lee-eun Yu, Youngsoo Shin: Statistical time borrowing for pulsed-latch circuit designs. ASP-DAC 2010: 675-680
10		Seungwhun Paik, Sangmin Kim, Youngsoo Shin: Wakeup synthesis and its buffered tree construction for power gating circuit designs. ISLPED 2010: 413-418
9		Hyein Lee, Seungwhun Paik, Youngsoo Shin: Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 355-366 (2010)
8		Seungwhun Paik, Insup Shin, Taewhan Kim, Youngsoo Shin: HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 657-670 (2010)
	2009
7		Insup Shin, Seungwhun Paik, Youngsoo Shin: Register allocation for high-level synthesis using dual supply voltages. DAC 2009: 937-942
6		Seungwhun Paik, Insup Shin, Youngsoo Shin: HLS-l: High-level synthesis of high performance latch-based circuits. DATE 2009: 1112-1117
5		Seonggwan Lee, Seungwhun Paik, Youngsoo Shin: Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits. ICCAD 2009: 375-380
4		Youngsoo Shin, Seungwhun Paik, Hyung-Ock Kim: Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 327-339 (2009)
	2008
3		Jinseob Jeong, Seungwhun Paik, Youngsoo Shin: Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation. ASP-DAC 2008: 629-634
2		Seungwhun Paik, Youngsoo Shin: Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements. DAC 2008: 600-605
1		Hyein Lee, Seungwhun Paik, Youngsoo Shin: Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits. ICCAD 2008: 224-229

Coauthor Index

1	Donkyu Baek	[17]
2	Inhak Han	[18]
3	Jinseob Jeong	[3]
4	Hyung-Ock Kim	[4]
5	Sangmin Kim	[10] [18]
6	Taewhan Kim	[8]
7	Hyein Lee	[1] [9]
8	Seonggwan Lee	[5] [14]
9	Jing-Jia Liou	[13]
10	Gi-Joon Nam	[16]
11	Jun Seomun	[12]
12	Changsik Shin	[13]
13	Dongwan Shin	[19]
14	Insup Shin	[6] [7] [8] [17] [19]
15	Youngsoo Shin	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
16	Lee-eun Yu	[11] [13]

Last update Sun Jun 3 16:06:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page