Hideki Osone

	2011
4		Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Takashi Miyoshi, Hideki Osone, Samir Parikh, Subodh M. Reddy, Toshiyuki Shibuya, Yasushi Umezawa, William W. Walker: A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel. ISSCC 2011: 346-348
	2009
3		Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone: A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control. ISSCC 2009: 188-189
	2007
2		Jian Hong Jiang, Weixin Gai, Akira Hattori, Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Hideki Osone: Design Consideration of 6.25 Gbps Signaling for High-Performance Server. ASP-DAC 2007: 854-857
	1995
1		Nirmal R. Saxena, Chien Chen, Ravi Swami, Hideki Osone, Shalesh Thusoo, David Lyon, David Chang, Anand Dharmaraj, Niteen Patkar, Yizhi Lu, Ben Chia: Error Detection and Handling in a Superscalar, Speculative Out-of-Order Execution Processor System. FTCS 1995: 464-471

Coauthor Index

1	David Chang	[1]
2	Chien Chen	[1]
3	Ben Chia	[1]
4	Anand Dharmaraj	[1]
5	Weixin Gai	[2] [3]
6	Akira Hattori	[2]
7	Yasuo Hidaka	[2] [3] [4]
8	Takeshi Horie	[2] [3] [4]
9	Jian Hong Jiang	[2] [3]
10	Yoichi Koyanagi	[2] [3] [4]
11	Yizhi Lu	[1]
12	David Lyon	[1]
13	Takashi Miyoshi	[4]
14	Samir Parikh	[4]
15	Niteen Patkar	[1]
16	Subodh M. Reddy	[4]
17	Nirmal R. Saxena	[1]
18	Toshiyuki Shibuya	[4]
19	Ravi Swami	[1]
20	Shalesh Thusoo	[1]
21	Yasushi Umezawa	[4]
22	William W. Walker	[4]

Colors in the list of coauthors

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