Máire O'Neill

Máire McLoone

	2011
33		Philip Hodgers, Keanhong Boey, Máire O'Neill: Power Spectral Density Side Channel Attack Overlapping Window Method. DSD 2011: 274-278
32		Weiqiang Liu, Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.: Design rules for Quantum-dot Cellular Automata. ISCAS 2011: 2361-2364
31		Xiaolin Cao, Máire O'Neill: A Forward Private Protocol based on PRNG and LPN for Low-cost RFID . SECRYPT 2011: 287-292
	2010
30		Brian Baldwin, Andrew Byrne, Liang Lu, Mark Hamilton, Neil Hanley, Máire O'Neill, William P. Marnane: FPGA Implementations of the Round Two SHA-3 Candidates. FPL 2010: 400-407
29		Yingxi Lu, Keanhong Boey, Philip Hodgers, Máire O'Neill: Lightweight DPA resistant solution on FPGA to counteract power models. FPT 2010: 178-183
28		Keanhong Boey, Philip Hodgers, Yingxi Lu, Máire O'Neill, Roger Woods: Security of AES Sbox designs to power analysis. ICECS 2010: 1232-1235
27		Keanhong Boey, Yingxi Lu, Máire O'Neill, Roger Woods: Differential Power Analysis of CAST-128. ISVLSI 2010: 143-148
26		Liang Lu, Weiqiang Liu, Máire O'Neill, Earl E. Swartzlander Jr.: QCA Systolic Matrix Multiplier. ISVLSI 2010: 149-154
25		Brian Baldwin, Andrew Byrne, Liang Lu, Mark Hamilton, Neil Hanley, Máire O'Neill, William P. Marnane: A Hardware Wrapper for the SHA-3 Hash Algorithms. IACR Cryptology ePrint Archive 2010: 124 (2010)
24		Jiang Wu, Máire O'Neill: On Foundation and Construction of Physical Unclonable Functions. IACR Cryptology ePrint Archive 2010: 171 (2010)
23		Máire O'Neill, Matthew J. B. Robshaw: Low-cost digital signature architecture suitable for radio frequency identification tags. IET Computers & Digital Techniques 4(1): 14-26 (2010)
22		Yingxi Lu, Máire O'Neill, John V. McCanny: Evaluation of Random Delay Insertion against DPA on FPGAs. TRETS 4(1): 11 (2010)
	2009
21		Yingxi Lu, Keanhong Boey, Máire O'Neill, John V. McCanny, Akashi Satoh: Is the differential frequency-based attack effective against random delay insertion? SiPS 2009: 051-056
20		Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.: ASIC evaluation of ECHO hash function. SoCC 2009: 387-390
19		Ghazanfar Ali Safdar, Máire O'Neill: Performance Analysis of Novel Randomly Shifted Certification Authority Authentication Protocol for MANETs. EURASIP J. Wireless Comm. and Networking 2009: (2009)
	2008
18		Yingxi Lu, Máire O'Neill, John V. McCanny: Differential Power Analysis of a SHACAL-2 hardware implementation. ISCAS 2008: 2933-2936
	2007
17		Máire McLoone, Matthew J. B. Robshaw: Public Key Cryptography and RFID Tags. CT-RSA 2007: 372-384
16		Máire McLoone, Matthew J. B. Robshaw: New Architectures for Low-Cost Public Key Cryptography on RFID Tags. ISCAS 2007: 1827-1830
15		Clare McGrath, Ghazanfar Ali Safdar, Máire McLoone: Identity Based Public Key Exchange (IDPKE) for Wireless Ad Hoc Networks. SECRYPT 2007: 167-170
14		Nicolas Sklavos, Máire McLoone, Xinmiao Zhang: MONET Special Issue on Next Generation Hardware Architectures for Secure Mobile Computing. MONET 12(4): 229-230 (2007)
13		Máire McLoone, Ciaran McIvor: High-speed & Low Area Hardware Architectures of the Whirlpool Hash Function. VLSI Signal Processing 47(1): 47-57 (2007)
	2006
12		Neil Smyth, Máire McLoone, John V. McCanny: An Adaptable And Scalable Asymmetric Cryptographic Processor. ASAP 2006: 341-346
11		Ghazanfar Ali Safdar, Clare McGrath, Máire McLoone: Limitations of existing wireless networks authentication and key management techniques for MANETs. ISCN 2006: 101-105
	2005
10		P. Moore, Máire McLoone, Sakir Sezer: Reconfigurable Instruction Interface Architecture for Private-Key Cryptography on the Altera Nios-II Processor. AICT/SAPIR/ELETE 2005: 296-299
9		Ciaran McIvor, Máire McLoone, John V. McCanny: High-Radix Systolic Modular Multiplication on Reconfigurable Hardware. FPT 2005: 13-18
8		Máire McLoone, Ciaran McIvor, Aidan Savage: High-Speed Hardware Architectures of the Whirlpool Hash Function. FPT 2005: 147-162
	2004
7		Ciaran McIvor, Máire McLoone, John V. McCanny: FPGA Montgomery Multiplier Architectures - A Comparison. FCCM 2004: 279-282
6		Ciaran McIvor, Máire McLoone, John V. McCanny: FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p). ISCAS (3) 2004: 509-512
	2003
5		Máire McLoone, John V. McCanny: Very High Speed 17 Gbps SHACAL Encryption Architecture. FPL 2003: 111-120
4		Ciaran McIvor, Máire McLoone, John V. McCanny: A high-speed, low latency RSA decryption silicon core. ISCAS (4) 2003: 133-136
3		Máire McLoone, John V. McCanny: Rijndael FPGA Implementations Utilising Look-Up Tables. VLSI Signal Processing 34(3): 261-275 (2003)
	2001
2		Máire McLoone, John V. McCanny: High Performance Single-Chip FPGA Rijndael Algorithm Implementations. CHES 2001: 65-76
1		Máire McLoone, John V. McCanny: Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm. FPL 2001: 152-161

Coauthor Index

1	Brian Baldwin	[25] [30]
2	Keanhong Boey	[21] [27] [28] [29] [33]
3	Andrew Byrne	[25] [30]
4	Xiaolin Cao	[31]
5	Mark Hamilton	[25] [30]
6	Neil Hanley	[25] [30]
7	Philip Hodgers	[28] [29] [33]
8	Weiqiang Liu	[26] [32]
9	Liang Lu	[20] [25] [26] [30] [32]
10	Yingxi Lu	[18] [21] [22] [27] [28] [29]
11	William P. Marnane (Liam Marnane)	[25] [30]
12	John V. McCanny	[1] [2] [3] [4] [5] [6] [7] [9] [12] [18] [21] [22]
13	Clare McGrath	[11] [15]
14	Ciaran McIvor	[4] [6] [7] [8] [9] [13]
15	P. Moore	[10]
16	Matthew J. B. Robshaw (Matthew Robshaw)	[16] [17] [23]
17	Ghazanfar Ali Safdar	[11] [15] [19]
18	Akashi Satoh	[21]
19	Aidan Savage	[8]
20	Sakir Sezer	[10]
21	Nicolas Sklavos	[14]
22	Neil Smyth	[12]
23	Earl E. Swartzlander Jr.	[20] [26] [32]
24	Roger Woods (Roger F. Woods)	[27] [28]
25	Jiang Wu	[24]
26	Xinmiao Zhang	[14]

Colors in the list of coauthors

Last update Sun Feb 12 22:50:56 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page