Maxime Nassar

	2012
13		Youssef Souissi, Shivam Bhasin, Sylvain Guilley, Maxime Nassar, Jean-Luc Danger: Towards Different Flavors of Combined Side Channel Attacks. CT-RSA 2012: 245-259
12		Maxime Nassar, Youssef Souissi, Sylvain Guilley, Jean-Luc Danger: RSM: A small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAs. DATE 2012: 1173-1178
	2011
11		Youssef Souissi, Jean-Luc Danger, Sylvain Guilley, Shivam Bhasin, Maxime Nassar: Embedded systems security: An evaluation methodology against Side Channel Attacks. DASIP 2011: 230-237
10		Maxime Nassar, Sylvain Guilley, Jean-Luc Danger: Formal Analysis of the Entropy / Security Trade-off in First-Order Masking Countermeasures against Side-Channel Attacks. INDOCRYPT 2011: 22-39
9		Maxime Nassar, Youssef Souissi, Sylvain Guilley, Jean-Luc Danger: "Rank Correction": A New Side-Channel Approach for Secret Key Recovery. InfoSecHiComNet 2011: 128-143
8		Maxime Nassar, Sylvain Guilley, Jean-Luc Danger: Formal Analysis of the Entropy / Security Trade-off in First-Order Masking Countermeasures against Side-Channel Attacks. IACR Cryptology ePrint Archive 2011: 534 (2011)
	2010
7		Maxime Nassar, Shivam Bhasin, Jean-Luc Danger, Guillaume Duc, Sylvain Guilley: BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation. DATE 2010: 849-854
6		Youssef Souissi, Maxime Nassar, Sylvain Guilley, Jean-Luc Danger, Florent Flament: First Principal Components Analysis: A New Side Channel Distinguisher. ICISC 2010: 407-419
5		Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu: Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics. Int. J. Reconfig. Comp. 2010: (2010)
	2009
4		Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar: Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints. DATE 2009: 640-645
3		Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane: Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig 2009: 213-218
2		Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu: DPL on Stratix II FPGA: What to Expect?. ReConFig 2009: 243-248
	2008
1		Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong: Place-and-Route Impact on the Security of DPL Designs in FPGAs. HOST 2008: 26-32

Coauthor Index

1	Shivam Bhasin	[3] [7] [11] [13]
2	Sumanta Chaudhuri	[1]
3	Jean-Luc Danger	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
4	Guillaume Duc	[7]
5	Florent Flament	[2] [3] [5] [6]
6	Tarik Graba	[1] [3]
7	Sylvain Guilley	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
8	Philippe Hoogvorst	[1]
9	Yves Mathieu	[2] [3] [4] [5]
10	Laurent Sauvage	[1] [2] [3] [4] [5]
11	Nidhal Selmane	[3]
12	Youssef Souissi	[6] [9] [11] [12] [13]
13	Vinh-Nga Vong	[1]

Last update Sun Jun 3 16:06:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page