G. N. Nandakumar

	2011
6		Santanu Bhowmick, S. Bhattacherjee, G. N. Nandakumar: Generation of Test Vectors for Sequential Cell Verification CoRR abs/1110.6105: (2011)
	2005
5		G. N. Nandakumar, Nirav Patel, Raghunatha Reddy, Makeshwar Kothandaraman: Application of Douglas-Peucker Algorithm to Generate Compact but Accurate IBIS Models. VLSI Design 2005: 757-761
	2004
4		Nirav Patel, M. Srihari, Pooja Maheswari, G. N. Nandakumar: An Efficient Method to Generate Test Vectors for Combinational Cell Verification. VLSI Design 2004: 769-772
	1998
3		Abhijit Das, Samrat Sen, Mohan Rangan, Rupesh Nayak, G. N. Nandakumar: False Path Detection at Transistor Level. VLSI Design 1998: 226-229
	1993
2		Ravindranath Naiknaware, G. N. Nandakumar, Srinivasa Rao Kasa: Automatic Test Plan Generation for Analog and Mixed Signal Integrated Circuits using Partial Activation and High Level Simulation. ITC 1993: 139-148
1		Ravindranath Naiknaware, G. N. Nandakumar, Rajeev Arora, John Larkin: Automatic Test Plan Generation for Analog Integrated Circuits - A Practical Approach. VLSI Design 1993: 140-143

Coauthor Index

1	Rajeev Arora	[1]
2	S. Bhattacherjee	[6]
3	Santanu Bhowmick	[6]
4	Abhijit Das	[3]
5	Srinivasa Rao Kasa	[2]
6	Makeshwar Kothandaraman	[5]
7	John Larkin	[1]
8	Pooja Maheswari	[4]
9	Ravindranath Naiknaware	[1] [2]
10	Rupesh Nayak	[3]
11	Nirav Patel	[4] [5]
12	Mohan Rangan	[3]
13	Raghunatha Reddy	[5]
14	Samrat Sen	[3]
15	M. Srihari	[4]

Colors in the list of coauthors

Last update Sun Jun 3 16:06:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page