Kazuteru Namba

	2012
31		Kentaroh Katoh, Kazuteru Namba, Hideo Ito: An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection. IEEE Trans. VLSI Syst. 20(5): 804-817 (2012)
	2011
30		Kazuteru Namba, Hideo Ito: Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits. IEEE Trans. Computers 60(10): 1459-1470 (2011)
29		Kazuteru Namba, Hideo Ito: Construction of BILBO FF with Soft-Error-Tolerant Capability. IEICE Transactions 94-D(5): 1045-1050 (2011)
	2010
28		Kentaroh Katoh, Kazuteru Namba, Hideo Ito: A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit. Asian Test Symposium 2010: 343-348
27		Masato Kitakami, Hiroshi Konno, Kazuteru Namba, Hideo Ito: Quantitative Evaluation of Integrity for Remote System Using the Internet. PRDC 2010: 229-230
26		Kazuteru Namba, Takashi Ikeda, Hideo Ito: Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing. IEEE Trans. VLSI Syst. 18(9): 1265-1276 (2010)
25		Kazuteru Namba, Kengo Nakashima, Hideo Ito: Single-Event-Upset Tolerant RS Flip-Flop with Small Area. IEICE Transactions 93-D(12): 3407-3409 (2010)
24		Kazuteru Namba, Hideo Ito: Chiba Scan Delay Fault Testing with Short Test Application Time. J. Electronic Testing 26(6): 667-677 (2010)
	2009
23		Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, Kazuteru Namba, Hideo Ito: A Delay Measurement Technique Using Signature Registers. Asian Test Symposium 2009: 157-162
22		Takumi Hoshi, Kazuteru Namba, Hideo Ito: Testing of Switch Blocks in Three-Dimensional FPGA. DFT 2009: 227-235
21		Masato Kitakami, Akihiro Katada, Kazuteru Namba, Hideo Ito: Dependability Evaluation for Internet-Based Remote Systems. PRDC 2009: 256-259
20		Kazuteru Namba, Hideo Ito: Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits. IEICE Transactions 92-A(9): 2295-2303 (2009)
19		Kazuteru Namba, Hideo Ito: Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding. IEICE Transactions 92-D(2): 269-282 (2009)
18		Kentaroh Katoh, Kazuteru Namba, Hideo Ito: Design for Delay Fault Testability of 2-Rail Logic Circuits. IEICE Transactions 92-D(2): 336-341 (2009)
17		Kentaroh Katoh, Kazuteru Namba, Hideo Ito: Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths. IEICE Transactions 92-D(3): 433-442 (2009)
16		Shuangyu Ruan, Kazuteru Namba, Hideo Ito: Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability. IEICE Transactions 92-D(8): 1534-1541 (2009)
15		Kazuteru Namba, Yoshikazu Matsui, Hideo Ito: Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding. J. Electronic Testing 25(1): 97-105 (2009)
	2008
14		Shuangyu Ruan, Kazuteru Namba, Hideo Ito: Soft Error Hardened FF Capable of Detecting Wide Error Pulse. DFT 2008: 272-280
13		Kazuteru Namba, Hideo Ito: Delay Fault Testability on Two-Rail Logic Circuits. DFT 2008: 482-490
12		Kazuteru Namba, Hideo Ito: Path Delay Fault Test Set for Two-Rail Logic Circuits. PRDC 2008: 347-348
11		Yoichi Sasaki, Kazuteru Namba, Hideo Ito: Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger. J. Electronic Testing 24(1-3): 11-19 (2008)
	2007
10		Takashi Ikeda, Kazuteru Namba, Hideo Ito: Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing. DFT 2007: 282-290
9		Kazuteru Namba, Eiji Fujiwara: Nonbinary single-symbol error correcting, adjacent two-symbol transposition error correcting codes over integer rings. Systems and Computers in Japan 38(8): 54-60 (2007)
	2006
8		Yoichi Sasaki, Kazuteru Namba, Hideo Ito: Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit. DFT 2006: 327-335
7		Kazuteru Namba, Hideo Ito: Proposal of Testable Multi-Context FPGA Architecture. IEICE Transactions 89-D(5): 1687-1693 (2006)
6		Kazuteru Namba, Hideo Ito: Redundant Design for Wallace Multiplier. IEICE Transactions 89-D(9): 2512-2524 (2006)
	2005
5		Kazuteru Namba, Hideo Ito: Design of Defect Tolerant Wallace Multiplier. PRDC 2005: 300-304
4		Kazuteru Namba, Hideo Ito: Scan Design for Two-Pattern Test without Extra Latches. IEICE Transactions 88-D(12): 2777-2785 (2005)
3		Kazuteru Namba, Hideo Ito: Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation. IEICE Transactions 88-D(9): 2135-2142 (2005)
	2001
2		Kazuteru Namba, Eiji Fujiwara: Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities. DFT 2001: 299-307
1		Kazuteru Namba, Eiji Fujiwara: A class of systematic m-ary single-symbol error correcting codes. Systems and Computers in Japan 32(6): 21-28 (2001)

Coauthor Index

1	Eiji Fujiwara	[1] [2] [9]
2	Takumi Hoshi	[22]
3	Takashi Ikeda	[10] [26]
4	Hideo Ito	[3] [4] [5] [6] [7] [8] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31]
5	Akihiro Katada	[21]
6	Kentaroh Katoh	[17] [18] [23] [28] [31]
7	Masato Kitakami	[21] [27]
8	Hiroshi Konno	[27]
9	Yoshikazu Matsui	[15]
10	Kengo Nakashima	[25]
11	Shuangyu Ruan	[14] [16]
12	Yoichi Sasaki	[8] [11]
13	Toru Tanabe	[23]
14	Haque Md Zahidul	[23]

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