Satyanand Nalam

	2011
9		Satyanand Nalam, Vikas Chandra, Robert C. Aitken, Benton H. Calhoun: Dynamic write limited minimum operating voltage for nanoscale SRAMs. DATE 2011: 467-472
8		Satyanand Nalam, Benton H. Calhoun: 5T SRAM With Asymmetric Sizing for Improved Read Stability. J. Solid-State Circuits 46(10): 2431-2442 (2011)
	2010
7		Jiajing Wang, Satyanand Nalam, Zhenyu Qi, Randy W. Mann, Mircea R. Stan, Benton H. Calhoun: Improving SRAM Vmin and yield by using variation-aware BTI stress. CICC 2010: 1-4
6		Satyanand Nalam, Mudit Bhargava, Ken Mai, Benton H. Calhoun: Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers. DAC 2010: 138-143
5		Randy W. Mann, Satyanand Nalam, Jiajing Wang, Benton H. Calhoun: Limits of bias based assist methods in nano-scale 6T SRAM. ISQED 2010: 1-8
4		Satyanand Nalam, Vikas Chandra, Cezary Pietrzyk, Robert C. Aitken, Benton H. Calhoun: Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation. ISQED 2010: 139-146
	2009
3		Satyanand Nalam, Benton H. Calhoun: Asymmetric sizing in a 45nm 5T SRAM to improve read stability over 6T. CICC 2009: 709-712
2		Satyanand Nalam, Mudit Bhargava, Kyle Ringgenberg, Ken Mai, Benton H. Calhoun: A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes. ICCD 2009: 523-528
	2008
1		Jiajing Wang, Satyanand Nalam, Benton H. Calhoun: Analyzing static and dynamic write margin for nanometer SRAMs. ISLPED 2008: 129-134

Coauthor Index

1	Robert C. Aitken (Rob Aitken)	[4] [9]
2	Mudit Bhargava	[2] [6]
3	Benton H. Calhoun	[1] [2] [3] [4] [5] [6] [7] [8] [9]
4	Vikas Chandra	[4] [9]
5	Ken Mai	[2] [6]
6	Randy W. Mann	[5] [7]
7	Cezary Pietrzyk	[4]
8	Zhenyu Qi	[7]
9	Kyle Ringgenberg	[2]
10	Mircea R. Stan	[7]
11	Jiajing Wang	[1] [5] [7]

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