Toru Nakura

	2012
23		Toru Nakura, Kunihiro Asada: Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter. IEICE Transactions 95-C(2): 297-302 (2012)
22		Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada: On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction. IEICE Transactions 95-C(4): 643-650 (2012)
	2011
21		Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada: All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. ASP-DAC 2011: 79-80
20		Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada: Decoupling capacitance boosting for on-chip resonant supply noise reduction. DDECS 2011: 111-114
19		Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada: On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure. ESSCIRC 2011: 183-186
18		Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada: All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter. IEICE Transactions 94-C(4): 487-494 (2011)
17		Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada: On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch. IEICE Transactions 94-C(4): 511-519 (2011)
16		Shingo Mandai, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Cascaded Time Difference Amplifier with Differential Logic Delay Cell. IEICE Transactions 94-C(4): 654-662 (2011)
15		Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada: 1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells. IEICE Transactions 94-C(6): 1098-1104 (2011)
	2010
14		Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada: Cascaded time difference amplifier using differential logic delay cell. ASP-DAC 2010: 355-356
13		Tetsuya Iizuka, Toru Nakura, Kunihiro Asada: Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects. DDECS 2010: 167-172
12		Benjamin Stefan Devlin, Toru Nakura, Makoto Ikeda, Kunihiro Asada: A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment. IEICE Transactions 93-A(7): 1319-1328 (2010)
11		Toru Nakura, Shingo Mandai, Makoto Ikeda, Kunihiro Asada: Time Difference Amplifier with Robust Gain Using Closed-Loop Control. IEICE Transactions 93-C(3): 303-308 (2010)
	2009
10		MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada: Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature. ACM Great Lakes Symposium on VLSI 2009: 177-180
9		Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda: Measurement of power supply noise tolerance of self-timed processor. DDECS 2009: 128-131
8		Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada: All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance. DDECS 2009: 206-209
7		Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada: Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability. IEICE Transactions 92-C(6): 798-805 (2009)
	2007
6		Taisuke Kazama, Toru Nakura, Makoto Ikeda, Kunihiro Asada: Design of Active Substrate Noise Canceller using Power Supply di/dt Detector. ASP-DAC 2007: 100-101
	2006
5		Toru Nakura, Makoto Ikeda, Kunihiro Asada: Autonomous di/dt Control of Power Supply for Margin Aware Operation. IEICE Transactions 89-C(11): 1689-1694 (2006)
4		Toru Nakura, Makoto Ikeda, Kunihiro Asada: Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply. IEICE Transactions 89-C(3): 364-369 (2006)
	2005
3		Toru Nakura, Makoto Ikeda, Kunihiro Asada: Stub vs. Capacitor for Power Supply Noise Reduction. IEICE Transactions 88-C(1): 125-132 (2005)
2		Toru Nakura, Makoto Ikeda, Kunihiro Asada: On-chip di/dt Detector Circuit. IEICE Transactions 88-C(5): 782-787 (2005)
1		Toru Nakura, Makoto Ikeda, Kunihiro Asada: Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs. IEICE Transactions 88-C(8): 1734-1739 (2005)

Coauthor Index

1	Kunihiro Asada	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23]
2	Sanad Bushnaq	[8]
3	Benjamin Stefan Devlin	[12]
4	Tetsuya Iizuka	[13] [15] [16] [18] [21]
5	Makoto Ikeda	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [14] [15] [16] [17] [18] [19] [20] [21] [22]
6	Koichiro Ishibashi	[17] [19] [20] [22]
7	Jaehyun Jeong	[18] [21]
8	MyeongGyu Jeong	[10]
9	Taisuke Kazama	[6]
10	Jinmyoung Kim	[17] [19] [20] [22]
11	Shingo Mandai	[7] [11] [14] [15] [16]
12	Taku Sogabe	[9]
13	Hidehiro Takata	[17] [19] [20] [22]

Last update Sun Jun 3 16:06:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page