 | 2007 |
|---|
| 5 |       | K. Najeeb,
Karthik Gururaj,
V. Kamakoti,
Vivekananda M. Vedula:
Controllability-driven Power Virus Generation for Digital Circuits.
VLSI Design 2007: 407-412 |
| 4 | | K. Najeeb,
Vishnu Vardhan Reddy Konda,
Siva Kumar Sastry Hari,
V. Kamakoti,
Vivekananda M. Vedula:
Power Virus Generation Using Behavioral Models of Circuits.
VTS 2007: 35-42 |
| 3 | | K. Najeeb,
Karthik Gururaj,
V. Kamakoti,
Vivekananda M. Vedula:
Controllability-Driven Peak Dynamic Power Estimation for VLSI Circuits.
J. Low Power Electronics 3(3): 280-292 (2007) |
| 2006 |
|---|
| 2 | | K. Najeeb,
Vishal Gupta,
V. Kamakoti,
Madhu Mutyam:
Delay and peak power minimization for on-chip buses using temporal redundancy.
ACM Great Lakes Symposium on VLSI 2006: 119-122 |
| 1 | | K. Najeeb,
Vishal Gupta,
V. Kamakoti,
Madhu Mutyam:
Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses.
J. Low Power Electronics 2(3): 425-436 (2006) |
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