 | 2011 |
|---|
| 8 |       | Lingamneni Avinash,
Christian C. Enz,
Jean-Luc Nagel,
Krishna V. Palem,
Christian Piguet:
Energy parsimonious circuit design through probabilistic pruning.
DATE 2011: 764-769 |
| 2010 |
|---|
| 7 | | Luca Benini,
Alberto Bocca,
Alberto Bonanno,
Alberto Macii,
Enrico Macii,
Jean-Luc Nagel,
Christian Piguet,
Massimo Poncino:
A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits.
J. Low Power Electronics 6(1): 44-55 (2010) |
| 2009 |
|---|
| 6 | | Pierre-François Ruedi,
Pascal Heim,
Steve Gyger,
François Kaess,
Claude Arm,
Ricardo Caseiro,
Jean-Luc Nagel,
Silvio Todeschini:
An SoC combining a 132dB QVGA pixel array and a 32b DSP/MCU processor for vision applications.
ISSCC 2009: 46-47 |
| 2008 |
|---|
| 5 | | Christian Piguet,
Jean-Luc Nagel,
Vincent Peiris,
Steve Gyger,
Daniel Séverac,
Marc Morgan,
Jean-Marc Masgonty:
Low-Power Heterogeneous Systems-on-Chips.
J. Low Power Electronics 4(2): 111-126 (2008) |
| 2006 |
|---|
| 4 | | Christian Schuster,
Jean-Luc Nagel,
Christian Piguet,
Pierre-André Farine:
Architectural and technology influence on the optimal total power consumption.
DATE 2006: 989-994 |
| 3 | | Christian Piguet,
Christian Schuster,
Jean-Luc Nagel:
Static and Dynamic Power Reduction by Architecture Selection.
PATMOS 2006: 659-668 |
| 2005 |
|---|
| 2 | | Christian Schuster,
Christian Piguet,
Jean-Luc Nagel,
Pierre-André Farine:
An Architecture Design Methodology for Minimal Total Power Consumption at Fixed Vdd and Vth.
J. Low Power Electronics 1(1): 3-10 (2005) |
| 2004 |
|---|
| 1 | | Christian Schuster,
Jean-Luc Nagel,
Christian Piguet,
Pierre-André Farine:
Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures.
PATMOS 2004: 169-178 |
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