Benoit Nadeau-Dostie

	2011
18		Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer: Power Aware Embedded Test. Asian Test Symposium 2011: 511-516
	2009
17		Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba: Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points. DFT 2009: 20-28
16		Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba: Test point insertion using functional flip-flops to drive control points. ITC 2009: 1-10
15		Benoit Nadeau-Dostie, Saman Adham, Russ Abbott: Improved Core Isolation and Access for Hierarchical Embedded Test. IEEE Design & Test of Computers 26(1): 18-25 (2009)
	2008
14		Benoit Nadeau-Dostie, Kiyoshi Takeshita, Jean-Francois Cote: Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks. ITC 2008: 1-10
	2006
13		Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie: OCI: Open Compression Interface. ITC 2006: 1-4
	2004
12		Saman Adham, Benoit Nadeau-Dostie: A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs. MTDT 2004: 98-101
	2002
11		Stephen K. Sunter, Benoit Nadeau-Dostie: Complete, Contactless I/O Testing - Reaching the Boundary in Minimizing Digital IC Testing Cost. ITC 2002: 446-455
	1999
10		Benoit Nadeau-Dostie, Jean-Francois Cote, Harry Hulvershorn, Stephen Pateras: An embedded technique for at-speed interconnect testing. ITC 1999: 431-438
9		Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie: Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1327-1340 (1999)
	1996
8		Bernd Könemann, Ben Bennetts, Najmi T. Jarwala, Benoit Nadeau-Dostie: Built-In Self-Test: Assuring System Integrity. IEEE Computer 29(11): 39-45 (1996)
	1995
7		Benoit Nadeau-Dostie, Harry Hulvershorn, Saman Adham: A New Hardware Fault Insertion Scheme for System Diagnostics Verification. ITC 1995: 994-1002
	1994
6		Benoit Nadeau-Dostie, Dwayne Burek, Abu S. M. Hassan: ScanBist: A Multifrequency Scan-Based BIST Method. IEEE Design & Test of Computers 11(1): 7-17 (1994)
	1992
5		Benoit Nadeau-Dostie, Dwayne Burek, Abu S. M. Hassan: ScanBIST: A Multi-frequency Scan-based BIST Method. ITC 1992: 506-513
4		Abu S. M. Hassan, Vinod K. Agarwal, Benoit Nadeau-Dostie, Janusz Rajski: BIST of PCB interconnects using boundary-scan architecture. IEEE Trans. on CAD of Integrated Circuits and Systems 11(10): 1278-1288 (1992)
	1990
3		Fidel Muradali, Vinod K. Agarwal, Benoit Nadeau-Dostie: A new procedure for weighted random built-in self-test. ITC 1990: 660-669
2		Benoit Nadeau-Dostie, Allan Silburt, Vinod K. Agarwal: Serial Interfacing for Embedded-Memory Testing. IEEE Design & Test of Computers 7(2): 52-63 (1990)
	1989
1		Abu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski, Benoit Nadeau-Dostie: Testing of Glue Logic Interconnects Using Boundary Scan Architecture. ITC 1989: 700-711

Coauthor Index

1	Russ Abbott	[15]
2	Saman Adham	[7] [12] [15]
3	Vinod K. Agarwal	[1] [2] [3] [4]
4	Ben Bennetts (R. G. Bennetts)	[8]
5	Samir Boubezari	[9]
6	Dwayne Burek	[5] [6] [13]
7	Eduard Cerny	[9]
8	Bruce Cory	[13]
9	Jean-Francois Cote	[10] [14]
10	Abu S. M. Hassan	[1] [4] [5] [6]
11	Harry Hulvershorn	[7] [10]
12	Najmi T. Jarwala	[8]
13	Bozena Kaminska	[9]
14	Rohit Kapur	[13]
15	Mark Kassab	[13]
16	Brion L. Keller	[13]
17	Kee Sup Kim	[13]
18	Bernd Könemann	[8]
19	Xijiang Lin	[18]
20	Elham K. Moghaddam	[18]
21	Nilanjan Mukherjee	[18]
22	Fidel Muradali	[3]
23	Steven F. Oakland	[13]
24	Stephen Pateras	[10]
25	Janusz Rajski	[1] [4] [18]
26	Allan Silburt	[2]
27	Stephen K. Sunter (Steve Sunter)	[11]
28	Kiyoshi Takeshita	[14]
29	Mick Tegethoff	[13]
30	Nur A. Touba	[16] [17]
31	Jerzy Tyszer	[18]
32	Joon-Sung Yang	[16] [17]

Colors in the list of coauthors

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