Chris J. Myers

	2011
75		Yingying Zhang, Emmanuel Rodriguez, Hao Zheng, Chris J. Myers: A Behavioral Analysis Approach for Efficient Partial Order Reduction. HASE 2011: 49-56
74		Scott Little, David Walter, Chris J. Myers, Robert Thacker, Satish Batchu, Tomohiro Yoneda: Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets. IEEE Trans. on CAD of Integrated Circuits and Systems 30(4): 617-630 (2011)
73		Nathan A. Barker, Chris J. Myers, Hiroyuki Kuwahara: Learning Genetic Regulatory Network Connectivity from Time Series Data. IEEE/ACM Trans. Comput. Biology Bioinform. 8(1): 152-165 (2011)
	2010
72		Haiqiong Yao, Hao Zheng, Chris J. Myers: State space reductions for scalable verification of asynchronous designs. HLDVT 2010: 17-24
71		Chris Winstead, Curtis Madsen, Chris J. Myers: iSSA: An incremental stochastic simulation algorithm for genetic circuits. ISCAS 2010: 553-556
70		Scott Little, David Walter, Kevin Jones, Chris J. Myers, Alper Sen: Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces. Int. J. Found. Comput. Sci. 21(2): 191-210 (2010)
69		Hiroyuki Kuwahara, Chris J. Myers, Michael S. Samoilov: Temperature Control of Fimbriation Circuit Switch in Uropathogenic Escherichia coli: Quantitative Analysis via Automated Model Abstraction. PLoS Computational Biology 6(3): (2010)
	2009
68		Chris J. Myers, Nathan A. Barker, Hiroyuki Kuwahara, Kevin Jones, Curtis Madsen, Nam-Phuong D. Nguyen: Genetic design automation. ICCAD 2009: 713-716
67		Robert Thacker, Chris J. Myers, Kevin Jones, Scott Little: A new verification method for embedded systems. ICCD 2009: 193-200
66		Chris J. Myers, Nathan A. Barker, Kevin Jones, Hiroyuki Kuwahara, Curtis Madsen, Nam-Phuong D. Nguyen: iBioSim: a tool for the analysis and design of genetic circuits. Bioinformatics 25(21): 2848-2849 (2009)
	2008
65		Naohiro Hamada, Yuuki Shiga, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya: A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper). ACSD 2008: 50-55
64		Frédéric Béal, Tomohiro Yoneda, Chris J. Myers: Hazard Checking of Timed Asynchronous Circuits Revisited. Fundam. Inform. 88(4): 411-435 (2008)
63		David Walter, Scott Little, Chris J. Myers, Nicholas Seegmiller, Tomohiro Yoneda: Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2223-2235 (2008)
62		Frédéric Béal, Tomohiro Yoneda, Chris J. Myers: A Conservative Framework for Safety-Failure Checking. IEICE Transactions 91-D(3): 642-654 (2008)
61		Hiroyuki Kuwahara, Chris J. Myers: Production-Passage-Time Approximation: A New Approximation Method to Accelerate the Simulation Process of Enzymatic Reactions. Journal of Computational Biology 15(7): 779-792 (2008)
	2007
60		Frédéric Béal, Tomohiro Yoneda, Chris J. Myers: Hazard Checking of Timed Asynchronous Circuits Revisited. ACSD 2007: 51-60
59		David Walter, Scott Little, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda: Symbolic Model Checking of Analog/Mixed-Signal Circuits. ASP-DAC 2007: 316-323
58		Nam-Phuong D. Nguyen, Hiroyuki Kuwahara, Chris J. Myers, James P. Keener: The Design of a Genetic Muller C-Element. ASYNC 2007: 95-104
57		Scott Little, David Walter, Kevin Jones, Chris J. Myers: Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces. ATVA 2007: 114-128
56		David Walter, Scott Little, Chris J. Myers: Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver. ATVA 2007: 66-81
55		Scott Little, Alper Sen, Chris J. Myers: Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits. MTV 2007: 109-115
54		Hiroyuki Kuwahara, Chris J. Myers: Production-Passage-Time Approximation: A New Approximation Method to Accelerate the Simulation Process of Enzymatic Reactions. RECOMB 2007: 166-180
53		Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda: Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 592-605 (2007)
52		Tomohiro Yoneda, Chris J. Myers: Synthesis of Timed Circuits Based on Decomposition. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1177-1195 (2007)
51		Hiroshi Saito, Naohiro Hamada, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya: Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times. IEICE Transactions 90-A(12): 2790-2799 (2007)
	2006
50		Tomohiro Yoneda, Chris J. Myers: Effective Contraction of Timed STGs for Decomposition Based Timed Circuit Synthesis. ATVA 2006: 229-244
49		Hiroyuki Kuwahara, Chris J. Myers, Michael S. Samoilov: Abstracted Stochastic Analysis of Type 1 Pili Expression in E.coli. BIOCOMP 2006: 125-134
48		Hiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya: ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation. CIT 2006: 172
47		Scott Little, Nicholas Seegmiller, David Walter, Chris J. Myers, Tomohiro Yoneda: Verification of analog/mixed-signal circuits using labeled hybrid petri nets. ICCAD 2006: 275-282
46		Nathan A. Barker, Chris J. Myers, Hiroyuki Kuwahara: Learning Genetic Regulatory Network Connectivity from Time Series Data. IEA/AIE 2006: 962-971
45		Chris J. Myers, Reid R. Harrison, David Walter, Nicholas Seegmiller, Scott Little: The Case for Analog Circuit Verification. Electr. Notes Theor. Comput. Sci. 153(3): 53-63 (2006)
44		Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda: Verification of timed circuits with failure-directed abstractions. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 403-412 (2006)
43		Hiroyuki Kuwahara, Chris J. Myers, Michael S. Samoilov, Nathan A. Barker, Adam P. Arkin: Automated Abstraction Methodology for Genetic Regulatory Networks. T. Comp. Sys. Biology: 150-175 (2006)
	2005
42		Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, Chris J. Myers: High Level Synthesis of Timed Asynchronous Circuits. ASYNC 2005: 178-189
41		Tomoya Kitai, Tomohiro Yoneda, Chris J. Myers: Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation. IEICE Transactions 88-D(11): 2555-2564 (2005)
40		Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers: Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. IEICE Transactions 88-D(7): 1646-1661 (2005)
	2004
39		Tomohiro Yoneda, Hiroomi Onda, Chris J. Myers: Synthesis of Speed Independent Circuits Based on Decomposition. ASYNC 2004: 135-145
38		Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers: Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. ATVA 2004: 339-353
37		Scott Little, David Walter, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda: Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets. ATVA 2004: 426-440
	2003
36		Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda: Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. ICCAD 2003: 424-432
35		Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda: Verification of Timed Circuits with Failure Directed Abstractions. ICCD 2003: 28-35
34		Hao Zheng, Eric Mercer, Chris J. Myers: Modular verification of timed circuits using automatic abstraction. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1138-1153 (2003)
	2002
33		Tomohiro Yoneda, Tomoya Kitai, Chris J. Myers: Automatic Derivation of Timing Constraints by Failure Analysis. CAV 2002: 195-208
32		Jie Dai, Chris Winstead, Chris J. Myers, Reid R. Harrison, Christian Schlegel: Cell library for automatic synthesis of analog error control decoders. ISCAS (4) 2002: 481-484
31		Tomoya Kitai, Yusuke Oguro, Tomohiro Yoneda, Eric Mercer, Chris J. Myers: Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method. PRDC 2002: 210-220
30		Eric Mercer, Chris J. Myers, Tomohiro Yoneda: Modular Synthesis of Timed Circuits using Partial Order Reduction. Electr. Notes Theor. Comput. Sci. 65(6): 180-201 (2002)
29		Hans M. Jacobson, Chris J. Myers: Efficient algorithms for exact two-level hazard-free logic minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1269-1283 (2002)
28		Sung Tae Jung, Chris J. Myers: Direct synthesis of timed circuits from free-choice STGs. IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 275-290 (2002)
	2001
27		Chris J. Myers: Asynchronous circuit design. Wiley 2001: I-XVII, 1-404
26		Chris Winstead, Jie Dai, Woo Jin Kim, Scott Little, Yong-Bin Kim, Chris J. Myers, Christian Schlegel: Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS. ARVLSI 2001: 132-147
25		Kip C. Killpack, Eric Mercer, Chris J. Myers: A Standard-Cell Self-Timed Multiplier for Energy and Area Critical Synchronous Systems. ARVLSI 2001: 188-201
24		Chris J. Myers, Wendy Belluomini, Kip Kallpack, Eric Peskin, Hao Zheng: Timed circuits: a new paradigm for high-speed design. ASP-DAC 2001: 335-340
23		Chris J. Myers, Hans M. Jacobson: Efficient Exact Two-Level Hazard-Free Logic Minimization. ASYNC 2001: 64-73
22		Bin Zhou, Tomohiro Yoneda, Chris J. Myers: Framework of Timed Trace Theoretic Verification Revisited. Asian Test Symposium 2001: 437-442
21		Hao Zheng, Eric Mercer, Chris J. Myers: Automatic Abstraction for Verification of Timed Circuits and Systems. CAV 2001: 182-193
20		Wendy Belluomini, Chris J. Myers, H. Peter Hofstee: Timed circuit verification using TEL structures. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 129-146 (2001)
	2000
19		Hans M. Jacobson, Chris J. Myers, Ganesh Gopalakrishnan: Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gC Finite State Machines. ICCAD 2000: 303-310
18		Allen E. Sjogren, Chris J. Myers: Interfacing synchronous and asynchronous modules within a high-speed pipeline. IEEE Trans. VLSI Syst. 8(5): 573-583 (2000)
17		Wendy Belluomini, Chris J. Myers: Timed state space exploration using POSETs. IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 501-520 (2000)
	1999
16		Wendy Belluomini, Chris J. Myers, H. Peter Hofstee: Verification of Delayed-Reset Domino Circuits Using ATACS. ASYNC 1999: 3-12
15		Shai Rotem, Ken S. Stevens, Charles Dike, Marly Roncken, Boris Agapiev, Ran Ginosar, Rakefet Kol, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun: RAPPID: An Asynchronous Instruction Length Decoder. ASYNC 1999: 60-70
14		Sung Tae Jung, Chris J. Myers: Direct synthesis of timed asynchronous circuits. ICCAD 1999: 332-338
13		Brandon M. Bachman, Hao Zheng, Chris J. Myers: Architectural Synthesis of Timed Asynchronous Systems. ICCD 1999: 354-363
12		Robert Thacker, Wendy Belluomini, Chris J. Myers: Timed Circuit Synthesis Using Implicit Methods. VLSI Design 1999: 181-188
11		Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng: POSET timing and its application to the synthesis and verification of gate-level timed circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 769-786 (1999)
	1998
10		Wei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun: Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. ASYNC 1998: 80-
9		Wendy Belluomini, Chris J. Myers: Verification of Timed Systems Using POSETs. CAV 1998: 403-415
8		Peter A. Beerel, Chris J. Myers, Teresa H. Y. Meng: Covering conditions and algorithms for the synthesis of speed-independent circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 205-219 (1998)
	1997
7		Allen E. Sjogren, Chris J. Myers: Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline. ARVLSI 1997: 47-61
6		Wendy Belluomini, Chris J. Myers: Efficient Timing Analysis Algorithms for Timed State Space Exploration. ASYNC 1997: 88-100
	1995
5		Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng: Automatic synthesis of gate-level timed circuits with choice. ARVLSI 1995: 42-58
4		Chris J. Myers, Peter A. Beerel, Teresa H. Y. Meng: Technology mapping of timed circuits. ASYNC 1995: 138-
	1994
3		Tomas Rokicki, Chris J. Myers: Automatic Verification of Timed Circuits. CAV 1994: 468-480
	1993
2		Chris J. Myers, Teresa H. Y. Meng: Synthesis of timed asynchronous circuits. IEEE Trans. VLSI Syst. 1(2): 106-119 (1993)
	1992
1		Chris J. Myers, Teresa H. Y. Meng: Synthesis of Timed Asynchronous Circuits. ICCD 1992: 279-284

Coauthor Index

1	Boris Agapiev	[15]
2	Adam P. Arkin	[43]
3	Brandon M. Bachman	[13]
4	Nathan A. Barker	[43] [46] [66] [68] [73]
5	Satish Batchu	[74]
6	Frédéric Béal	[60] [62] [64]
7	Peter A. Beerel	[4] [8] [10] [15]
8	Wendy Belluomini	[6] [9] [12] [16] [17] [20] [24]
9	Wei-Chun Chou	[10]
10	Jie Dai	[26] [32]
11	Charles Dike	[15]
12	Ran Ginosar	[10] [15]
13	Ganesh Gopalakrishnan	[19]
14	Naohiro Hamada	[51] [65]
15	Reid R. Harrison	[32] [45]
16	H. Peter Hofstee	[16] [20]
17	Hans M. Jacobson	[19] [23] [29]
18	Nattha Jindapetch	[48] [51]
19	Kevin Jones	[57] [66] [67] [68] [70]
20	Sung Tae Jung	[14] [28]
21	Kip Kallpack	[24]
22	Manabu Kato	[42]
23	James P. Keener	[58]
24	Kip C. Killpack	[25]
25	Woo Jin Kim	[26]
26	Yong-Bin Kim	[26]
27	Tomoya Kitai	[31] [33] [41]
28	Rakefet Kol	[10] [15]
29	Hiroyuki Kuwahara	[43] [46] [49] [54] [58] [61] [66] [68] [69] [73]
30	Scott Little	[26] [35] [37] [44] [45] [47] [55] [56] [57] [59] [63] [67] [70] [74]
31	Curtis Madsen	[66] [68] [71]
32	Atsushi Matsumoto	[42]
33	Teresa H. Y. Meng	[1] [2] [4] [5] [8] [11]
34	Eric Mercer (Eric G. Mercer)	[21] [25] [30] [31] [34]
35	Takashi Nanya	[48] [51] [65]
36	Curtis A. Nelson	[36] [53]
37	Nam-Phuong D. Nguyen	[58] [66] [68]
38	Yusuke Oguro	[31]
39	Hiroomi Onda	[39]
40	Eric Peskin	[24]
41	Denduang Pradubsuwun	[38] [40]
42	Emmanuel Rodriguez	[75]
43	Tomas Rokicki	[3] [5] [11]
44	Marly Roncken	[15]
45	Shai Rotem	[10] [15]
46	Hiroshi Saito	[48] [51] [65]
47	Michael S. Samoilov	[43] [49] [69]
48	Christian Schlegel	[26] [32]
49	Nicholas Seegmiller	[37] [45] [47] [59] [63]
50	Alper Sen	[55] [70]
51	Yuuki Shiga	[65]
52	Allen E. Sjogren	[7] [18]
53	Kenneth S. Stevens (Ken S. Stevens)	[10] [15]
54	Robert Thacker	[12] [67] [74]
55	David Walter	[35] [37] [44] [45] [47] [56] [57] [59] [63] [70] [74]
56	Chris Winstead	[26] [32] [71]
57	Haiqiong Yao	[72]
58	Tomohiro Yoneda	[22] [30] [31] [33] [35] [36] [37] [38] [39] [40] [41] [42] [44] [47] [48] [50] [51] [52] [53] [59] [60] [62] [63] [64] [65] [74]
59	Kenneth Y. Yun	[10] [15]
60	Yingying Zhang	[75]
61	Hao Zheng (Hank Jayne)	[13] [21] [24] [34] [35] [44] [72] [75]
62	Bin Zhou	[22]

Colors in the list of coauthors

Last update Mon Jun 4 20:40:43 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page