 | 2000 |
| 9 |  | Annette Muth,
Thomas Kolloch,
Thomas Maier-Komor,
Georg Färber:
An Evaluation of Code Generation Strategies Targeting Hardware for the Rapid Prototyping of SDL-Specifications.
IEEE International Workshop on Rapid System Prototyping 2000: 134- |
| 8 |  | Annette Muth,
Georg Färber:
SDL as a System Level Specification Language for Application-Specific Hardware in a Rapid Prototyping Environment.
ISSS 2000: 157-162 |
| 7 |  | Stefan M. Petters,
Annette Muth,
Thomas Kolloch,
Thomas Hopfner,
Franz Fischer,
Georg Färber:
The REAR Framework for Emulation and Analysis of Embedded Hard Real-Time Systems.
Design Autom. for Emb. Sys. 5(3-4): 237-250 (2000) |
| 6 |  | Franz Fischer,
Thomas Hopfner,
Thomas Kolloch,
Annette Muth,
Stefan M. Petters,
Georg Färber,
Matthias Dörfel,
Winfried Dulz,
Richard Hofmann,
Andreas Mitschele-Thiel,
Ralf Münzenberger,
Frank Slomka:
Rapid Prototyping von Realzeitsystemen mit SDL (Rapid Prototyping of Real Time Systems using SDL).
it+ti - Informationstechnik und Technische Informatik 42(2): 45-53 (2000) |
| 1999 |
| 5 |  | Stefan M. Petters,
Annette Muth,
Thomas Kolloch,
Thomas Hopfner,
Franz Fischer,
Georg Färber:
The REAR Framework for Emulation and Analysis of Embedded Hard Real-Time Systems .
IEEE International Workshop on Rapid System Prototyping 1999: 100-107 |
| 4 |  | Oliver Bringmann,
Wolfgang Rosenstiel,
Annette Muth,
Georg Färber,
Frank Slomka,
Richard Hofmann:
Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping.
IEEE International Workshop on Rapid System Prototyping 1999: 114-119 |
| 1998 |
| 3 |  | Franz Fischer,
Annette Muth,
Georg Färber:
Towards interprocess communication and interface synthesis for a heterogeneous real-time rapid prototyping environment.
CODES 1998: 35-39 |
| 1997 |
| 2 |  | Franz Fischer,
Thomas Kolloch,
Annette Muth,
Georg Färber:
A Configurable Target Architecture for Rapid Prototyping High Performance Control Systems.
PDPTA 1997: 1382-1390 |
| 1 |  | Georg Färber,
Franz Fischer,
Thomas Kolloch,
Annette Muth:
Improving processor utilization with a task classification model based application specific hard real-time architecture.
RTCSA 1997: 276- |