 | 2011 |
| 20 |  | Rajeev Balasubramonian,
Norman P. Jouppi,
Naveen Muralimanohar:
Multi-Core Cache Hierarchies
Morgan & Claypool Publishers 2011 |
| 19 |  | Doe Hyun Yoon,
Naveen Muralimanohar,
Jichuan Chang,
Parthasarathy Ranganathan,
Norman P. Jouppi,
Mattan Erez:
FREE-p: Protecting non-volatile memory against both hard and soft errors.
HPCA 2011: 466-477 |
| 18 |  | Aniruddha N. Udipi,
Naveen Muralimanohar,
Rajeev Balasubramonian,
Al Davis,
Norman P. Jouppi:
Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems.
ISCA 2011: 425-436 |
| 17 |  | Nathan L. Binkert,
Al Davis,
Norman P. Jouppi,
Moray McLaren,
Naveen Muralimanohar,
Robert Schreiber,
Jung Ho Ahn:
The role of optics in future high radix switch design.
ISCA 2011: 437-448 |
| 16 |  | Sheng Li,
Ke Chen,
Ming-yu Hsieh,
Naveen Muralimanohar,
Chad D. Kersey,
Jay B. Brockman,
Arun F. Rodrigues,
Norman P. Jouppi:
System implications of memory reliability in exascale computing.
SC 2011: 46 |
| 15 |  | Xiangyu Dong,
Yuan Xie,
Naveen Muralimanohar,
Norman P. Jouppi:
Hybrid checkpointing using emerging nonvolatile memories for future exascale systems.
TACO 8(2): 6 (2011) |
| 2010 |
| 14 |  | Aniruddha N. Udipi,
Naveen Muralimanohar,
Rajeev Balasubramonian:
Towards scalable, energy-efficient, bus-based on-chip networks.
HPCA 2010: 1-12 |
| 13 |  | Aniruddha N. Udipi,
Naveen Muralimanohar,
Niladrish Chatterjee,
Rajeev Balasubramonian,
Al Davis,
Norman P. Jouppi:
Rethinking DRAM design and organization for energy-constrained multi-cores.
ISCA 2010: 175-186 |
| 12 |  | Xiangyu Dong,
Yuan Xie,
Naveen Muralimanohar,
Norman P. Jouppi:
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support.
SC 2010: 1-11 |
| 2009 |
| 11 |  | Niti Madan,
Li Zhao,
Naveen Muralimanohar,
Aniruddha N. Udipi,
Rajeev Balasubramonian,
Ravishankar Iyer,
Srihari Makineni,
Donald Newell:
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy.
HPCA 2009: 262-274 |
| 10 |  | Aniruddha N. Udipi,
Naveen Muralimanohar,
Rajeev Balasubramonian:
Non-uniform power access in large caches with low-swing wires.
HiPC 2009: 59-68 |
| 9 |  | Xiangyu Dong,
Naveen Muralimanohar,
Norman P. Jouppi,
Richard Kaufmann,
Yuan Xie:
Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems.
SC 2009 |
| 2008 |
| 8 |  | Seth H. Pugsley,
Manu Awasthi,
Niti Madan,
Naveen Muralimanohar,
Rajeev Balasubramonian:
Scalable and reliable communication for hardware transactional memory.
PACT 2008: 144-154 |
| 7 |  | Naveen Muralimanohar,
Rajeev Balasubramonian,
Norman P. Jouppi:
Architecting Efficient Interconnects for Large Caches with CACTI 6.0.
IEEE Micro 28(1): 69-79 (2008) |
| 2007 |
| 6 |  | Naveen Muralimanohar,
Rajeev Balasubramonian:
Interconnect design considerations for large NUCA caches.
ISCA 2007: 369-380 |
| 5 |  | Naveen Muralimanohar,
Rajeev Balasubramonian,
Norman P. Jouppi:
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0.
MICRO 2007: 3-14 |
| 2006 |
| 4 |  | Liqun Cheng,
Naveen Muralimanohar,
Karthik Ramani,
Rajeev Balasubramonian,
John B. Carter:
Interconnect-Aware Coherence Protocols for Chip Multiprocessors.
ISCA 2006: 339-351 |
| 3 |  | Naveen Muralimanohar,
Karthik Ramani,
Rajeev Balasubramonian:
Power efficient resource scaling in partitioned architectures through dynamic heterogeneity.
ISPASS 2006: 100-111 |
| 2 |  | Rajeev Balasubramonian,
Naveen Muralimanohar,
Karthik Ramani,
Liqun Cheng,
John B. Carter:
Leveraging Wire Properties at the Microarchitecture Level.
IEEE Micro 26(6): 40-52 (2006) |
| 2005 |
| 1 |  | Rajeev Balasubramonian,
Naveen Muralimanohar,
Karthik Ramani,
Venkatanand Venkatachalapathy:
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures.
HPCA 2005: 28-39 |