 | 1993 |
|---|
| 9 |       | Yasushi Koseko,
Takuji Ogihara,
Shinichi Murai:
Tri-state bus conflict checking method for ATPG using BDD.
ICCAD 1993: 512-515 |
| 1989 |
|---|
| 8 | | Takuji Ogihara,
K. Muroi,
Genichi Yonemori,
Shinichi Murai:
MULTES/IS: An Effective and Reliable Test Generation System for Partial Scan and Non-Scan Synchronous Circuits.
DAC 1989: 519-524 |
| 1987 |
|---|
| 7 | | Takuji Ogihara,
H. Toyoshima,
Shinichi Murai:
ASTA: LSI Design Management System.
DAC 1987: 530-536 |
| 1985 |
|---|
| 6 | | Takuji Ogihara,
Shuichi Saruyama,
Shinichi Murai:
PATEGE: an automatic DC parametric test generation system for series gated ECL circuits.
DAC 1985: 212-218 |
| 1983 |
|---|
| 5 | | Takuji Ogihara,
Shinichi Murai,
Yuzo Takamatsu,
Kozo Kinoshita,
Hideo Fujiwara:
Test generation for scan design circuits with tri-state modules and bidirectional terminals.
DAC 1983: 71-78 |
| 1981 |
|---|
| 4 | | Chiyoji Tanaka,
Shinichi Murai,
Shunichiro Nakamura,
Takuji Ogihara,
Masayuki Terai,
Kozo Kinoshita:
An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2.
DAC 1981: 59-65 |
| 3 | | Chiyoji Tanaka,
Shinichi Murai,
Hiroo Tsuji,
Toshihiko Yahara,
Kaoru Okazaki,
Masayuki Terai,
Reiji Katoh,
Mikio Tachibana:
An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3.
DAC 1981: 812-819 |
| 1979 |
|---|
| 2 | | Shinichi Murai,
Hiroo Tsuji,
Morio Kakinuma,
Kazumichi Sakaguchi,
Chiyoji Tanaka:
A hierarchical placement procedure with a simple blocking scheme.
DAC 1979: 18-23 |
| 1978 |
|---|
| 1 | | Shunichiro Nakamura,
Shinichi Murai,
Chiyoji Tanaka,
Masayuki Terai,
Hideo Fujiwara,
Kozo Kinoshita:
LORES - Logic Reorganization System.
DAC 1978: 250-260 |
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