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Fukashi Morishita Coauthor index pubzone.org

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DBLP keys2009
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto: On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform. IEICE Transactions 92-C(3): 356-363 (2009)
2007
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto: A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform. IEICE Transactions 90-C(10): 1927-1935 (2007)
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLFukashi Morishita, Hideyuki Noda, Isamu Hayashi, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto: A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI. IEICE Transactions 90-C(4): 765-771 (2007)
2006
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTakayuki Gyohten, Fukashi Morishita, Isamu Hayashi, Mako Okamoto, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Yasutaka Horiba: An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design. IEICE Transactions 89-C(11): 1519-1525 (2006)
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHideyuki Noda, Katsumi Dosaka, Hans Jürgen Mattausch, Tetsushi Koide, Fukashi Morishita, Kazutami Arimoto: A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. IEICE Transactions 89-C(11): 1612-1619 (2006)
2005
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAkira Yamazaki, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara: A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. IEICE Transactions 88-C(10): 2020-2027 (2005)

Coauthor Index

1Teruhiko Amano [1]
2Kazutami Arimoto [1] [2] [3] [4] [5] [6]
3Katsumi Dosaka [1] [2] [3] [4] [5] [6]
4Takayuki Gyohten [3] [4]
5Atsushi Hachisuka [1]
6Masaru Haraguchi [1]
7Isamu Hayashi [3] [4]
8Yasutaka Horiba [3]
9Takashi Ipposhi [4]
10Tetsushi Koide [2]
11Shigeto Maegawa [4]
12Hans Jürgen Mattausch [2]
13Hideyuki Noda [1] [2] [3] [4]
14Mako Okamoto [3] [4]
15Hideyuki Ozaki [1]
16Hiroki Shimano [5] [6]
17Setsuo Wake [1]
18Naoya Watanabe [1]
19Akira Yamazaki [1]
20Tsutomu Yoshihara [1]

Last update Sun Jun 3 16:06:10 2012 CET by the DBLP TeamThis material is Open Data Data released under the ODC-BY 1.0 license — See also our legal information page