Sumio Morioka

	2011
14		Sumio Morioka, Toshiyuki Isshiki, Satoshi Obana, Yuichi Nakamura, Kazue Sako: Flexible architecture optimization and ASIC implementation of group signature algorithm using a customized HLS methodology. HOST 2011: 57-62
	2004
13		Sumio Morioka, Akashi Satoh: A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. IEEE Trans. VLSI Syst. 12(7): 686-691 (2004)
	2003
12		Akashi Satoh, Sumio Morioka: Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia. CHES 2003: 304-318
11		Akashi Satoh, Sumio Morioka: Hardware-Focused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES. ISC 2003: 252-266
	2002
10		Sumio Morioka, Akashi Satoh: An Optimized S-Box Circuit Architecture for Low Power AES Design. CHES 2002: 172-186
9		Sumio Morioka, Akashi Satoh: A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture. ICCD 2002: 98-103
8		Akashi Satoh, Sumio Morioka: Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI. ISC 2002: 48-62
	2001
7		Akashi Satoh, Sumio Morioka, Kohji Takano, Seiji Munetoh: A Compact Rijndael Hardware Architecture with S-Box Optimization. ASIACRYPT 2001: 239-254
6		Sumio Morioka, Yasunao Katayama, Toshiyuki Yamane: Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2m). CAV 2001: 465-477
	2000
5		Yasunao Katayama, Yasushi Negishi, Sumio Morioka: Efficient Error Correction Code Configurations for Quasi-Nonvolatile Data Retention by DRAMs. DFT 2000: 201-
4		Yasunao Katayama, Sumio Morioka: One-Shot Reed-Solomon Decoding for High-Performance Dependable Systems. DSN 2000: 390-399
	1999
3		Yasunao Katayama, Eric J. Stuckey, Sumio Morioka, Zhao Wu: Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention. DFT 1999: 311-318
2		Sumio Morioka, Yasunao Katayama: Design Methodology for a One-Shot Reed-Solomon Encoder and Decoder. ICCD 1999: 60-67
	1994
1		Junji Kitamichi, Sumio Morioka, Teruo Higashino, Kenichi Taniguchi: Automatic Correctness Proof of the Implementation of Synchronous Sequential Circuits Using an Algebraic Approach. TPCD 1994: 165-184

Coauthor Index

1	Teruo Higashino	[1]
2	Toshiyuki Isshiki	[14]
3	Yasunao Katayama	[2] [3] [4] [5] [6]
4	Junji Kitamichi	[1]
5	Seiji Munetoh	[7]
6	Yuichi Nakamura (Yuhichi Nakamura)	[14]
7	Yasushi Negishi	[5]
8	Satoshi Obana	[14]
9	Kazue Sako	[14]
10	Akashi Satoh	[7] [8] [9] [10] [11] [12] [13]
11	Eric J. Stuckey	[3]
12	Kohji Takano	[7]
13	Kenichi Taniguchi	[1]
14	Zhao Wu	[3]
15	Toshiyuki Yamane	[6]

Colors in the list of coauthors

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