 | 2009 |
|---|
| 4 |       | Shigenobu Komatsu,
Masanao Yamaoka,
Masao Morimoto,
Noriaki Maeda,
Yasuhisa Shimazaki,
Kenichi Osada:
A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation.
CICC 2009: 701-704 |
| 2007 |
|---|
| 3 | | Masao Morimoto,
Makoto Nagata,
Kazuo Taki:
Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations.
IEICE Transactions 90-C(4): 675-682 (2007) |
| 2005 |
|---|
| 2 | | Masao Morimoto,
Yoshinori Tanaka,
Makoto Nagata,
Kazuo Taki:
Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition.
IEICE Transactions 88-A(12): 3324-3331 (2005) |
| 1 | | Masao Morimoto,
Makoto Nagata,
Kazuo Taki:
High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition.
IEICE Transactions 88-C(10): 2001-2008 (2005) |
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