Teresa Monreal

	2009
9		Darío Suárez Gracia, Teresa Monreal, Fernando Vallejo, Ramón Beivide, Víctor Viñals: Light NUCA: A proposal for bridging the inter-cache latency gap. DATE 2009: 530-535
	2008
8		Jesús Alastruey, Teresa Monreal, Francisco J. Cazorla, Víctor Viñals, Mateo Valero: Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. SBAC-PAD 2008: 63-70
	2007
7		Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero: Microarchitectural Support for Speculative Register Renaming. IPDPS 2007: 1-10
	2006
6		Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero: Speculative early register release. Conf. Computing Frontiers 2006: 291-302
	2005
5		Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero: Hardware support for early register release. IJHPCN 3(2/3): 83-94 (2005)
	2004
4		Teresa Monreal, Víctor Viñals, José González, Antonio González, Mateo Valero: Late Allocation and Early Release of Physical Registers. IEEE Trans. Computers 53(10): 1244-1259 (2004)
	2002
3		Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero: Hardware Schemes for Early Register Release. ICPP 2002: 5-13
	2000
2		Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals: Dynamic Register Renaming Through Virtual-Physical Registers. J. Instruction-Level Parallelism 2: (2000)
	1999
1		Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals: Delaying Physical Register Allocation through Virtual-Physical Registers. MICRO 1999: 186-

Coauthor Index

1	Jesús Alastruey	[6] [7] [8]
2	Ramón Beivide	[9]
3	Francisco J. Cazorla (Francisco J. Cazorla-Almeida)	[8]
4	Antonio González	[1] [2] [3] [4] [5]
5	José González	[1] [2] [4]
6	Darío Suárez Gracia	[9]
7	Mateo Valero	[1] [2] [3] [4] [5] [6] [7] [8]
8	Fernando Vallejo	[9]
9	Víctor Viñals (Víctor Viñals Yúfera)	[1] [2] [3] [4] [5] [6] [7] [8] [9]

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