 | 2011 |
|---|
| 10 |       | H. Gregor Molter,
André Seffrin,
Sorin A. Huss:
State space optimization within the DEVS model of computation for timing efficiency.
VLSI-SoC 2011: 422-427 |
| 9 | | H. Gregor Molter,
Marc Stöttinger,
Abdulhadi Shoufan,
Falko Strenzke:
A simple power analysis attack on a McEliece cryptoprocessor.
J. Cryptographic Engineering 1(1): 29-36 (2011) |
| 8 | | Abdulhadi Shoufan,
Nico Huber,
H. Gregor Molter:
A novel cryptoprocessor architecture for chained Merkle signature scheme.
Microprocessors and Microsystems - Embedded Hardware Design 35(1): 34-47 (2011) |
| 2010 |
|---|
| 7 | | Abdulhadi Shoufan,
Thorsten Wink,
H. Gregor Molter,
Sorin A. Huss,
Eike Kohnert:
A Novel Cryptoprocessor Architecture for the McEliece Public-Key Cryptosystem.
IEEE Trans. Computers 59(11): 1533-1546 (2010) |
| 2009 |
|---|
| 6 | | Abdulhadi Shoufan,
Thorsten Wink,
H. Gregor Molter,
Sorin A. Huss,
Falko Strenzke:
A Novel Processor Architecture for McEliece Cryptosystem and FPGA Platforms.
ASAP 2009: 98-105 |
| 5 | | Felix Madlener,
H. Gregor Molter,
Sorin A. Huss:
SC-DEVS: An efficient SystemC extension for the DEVS model of computation.
DATE 2009: 1518-1523 |
| 4 | | H. Gregor Molter,
André Seffrin,
Sorin Alexander Huss:
DEVS2VHDL: Automatic transformation of XML-specified DEVS Model of Computation into synthesizable VHDL code.
FDL 2009: 1-6 |
| 3 | | Abdulhadi Shoufan,
Falko Strenzke,
H. Gregor Molter,
Marc Stöttinger:
A Timing Attack against Patterson Algorithm in the McEliece PKC.
ICISC 2009: 161-175 |
| 2008 |
|---|
| 2 | | Ralf Laue,
H. Gregor Molter,
Felix Rieder,
Sorin A. Huss,
Kartik Saxena:
A Novel Multiple Core Co-processor Architecture for Efficient Server-Based Public Key Cryptographic Applications.
ISVLSI 2008: 87-92 |
| 1 | | Falko Strenzke,
Erik Tews,
H. Gregor Molter,
Raphael Overbeck,
Abdulhadi Shoufan:
Side Channels in the McEliece PKC.
PQCrypto 2008: 216-229 |
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