 | 2011 |
| 16 |  | Dieter F. Wendel,
Ronald N. Kalla,
James D. Warnock,
Robert Cargnoni,
Sam G. Chu,
Joachim G. Clabes,
Daniel Dreps,
David Hrusecky,
Joshua Friedrich,
Md. Saiful Islam,
James A. Kahle,
Jens Leenstra,
Gaurav Mittal,
Jose Paredes,
Juergen Pille,
Phillip J. Restle,
Balaram Sinharoy,
George Smith,
William J. Starke,
Scott Taylor,
James Van Norstrand,
Stephen Weitzel,
Phillip G. Williams,
Victor V. Zyuban:
POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor.
J. Solid-State Circuits 46(1): 145-161 (2011) |
| 2010 |
| 15 |  | Lei Gao,
David Zaretsky,
Gaurav Mittal,
Dan Schonfeld,
Prith Banerjee:
Automatic Generation of Stream Descriptors for Streaming Architectures.
ICPP 2010: 307-312 |
| 2009 |
| 14 |  | Gaurav Mittal,
David Zaretsky,
Prithviraj Banerjee:
Streaming implementation of a sequential decompression algorithm on an FPGA.
FPGA 2009: 283 |
| 13 |  | Lei Gao,
Gaurav Mittal,
David Zaretsky,
Dan Schonfeld,
Prithviraj Banerjee:
An Automated Algorithm to Generate Stream Programs.
ISCAS 2009: 1505-1508 |
| 12 |  | David Zaretsky,
Gaurav Mittal,
Prithviraj Banerjee:
Streaming Implementation of the ZLIB Decoder Algorithm on an FPGA.
ISCAS 2009: 2329-2332 |
| 11 |  | Lei Gao,
David Zaretsky,
Gaurav Mittal,
Dan Schonfeld,
Prith Banerjee:
A software pipelining algorithm in high-level synthesis for FPGA architectures.
ISQED 2009: 297-302 |
| 2007 |
| 10 |  | David Zaretsky,
Gaurav Mittal,
Robert P. Dick,
Prith Banerjee:
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs.
ISQED 2007: 595-601 |
| 9 |  | Gaurav Mittal,
David Zaretsky,
Xiaoyong Tang,
Prithviraj Banerjee:
An Overview of a Compiler for Mapping Software Binaries to Hardware.
IEEE Trans. VLSI Syst. 15(11): 1177-1190 (2007) |
| 2006 |
| 8 |  | Gaurav Mittal,
Sushrutha Locharam,
Sreela Sasi,
Glenn R. Shaffer,
Ajith K. Kumar:
An Efficient Video Enhancement Method Using LA*B* Analysis.
AVSS 2006: 66 |
| 7 |  | Gaurav Mittal,
Sreela Sasi:
Robust Preprocessing Algorithm for Face Recognition.
CRV 2006: 57 |
| 6 |  | David Zaretsky,
Gaurav Mittal,
Robert P. Dick,
Prith Banerjee:
Dynamic Template Generation for Resource Sharing in Control and Data Flow Graphs.
VLSI Design 2006: 465-468 |
| 2005 |
| 5 |  | Gaurav Mittal,
David Zaretsky,
Gokhan Memik,
Prith Banerjee:
Automatic extraction of function bodies from software binaries.
ASP-DAC 2005: 928-931 |
| 4 |  | David Zaretsky,
Gaurav Mittal,
Robert P. Dick,
Prith Banerjee:
Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code.
LCPC 2005: 76-90 |
| 2004 |
| 3 |  | David Zaretsky,
Gaurav Mittal,
Xiaoyong Tang,
Prithviraj Banerjee:
Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs.
ACM Great Lakes Symposium on VLSI 2004: 397-400 |
| 2 |  | Gaurav Mittal,
David Zaretsky,
Xiaoyong Tang,
Prithviraj Banerjee:
Automatic translation of software binaries onto FPGAs.
DAC 2004: 389-394 |
| 1 |  | David Zaretsky,
Gaurav Mittal,
Xiaoyong Tang,
Prithviraj Banerjee:
Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs.
FCCM 2004: 37-46 |