Yukio Mitsuyama

	2012
23		Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits. IEEE Trans. VLSI Syst. 20(2): 333-343 (2012)
	2011
22		Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye: Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures. FPL 2011: 189-194
21		Toshihiro Kameda, Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye: NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode. PATMOS 2011: 152-161
20		Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye: Stress Probability Computation for Estimating NBTI-Induced Delay Degradation. IEICE Transactions 94-A(12): 2545-2553 (2011)
	2010
19		Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits. ASP-DAC 2010: 361-362
18		Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye: Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration. ISQED 2010: 646-651
17		Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye: Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution. ISQED 2010: 839-844
16		Takehiko Amaki, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling. WISA 2010: 107-121
15		Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits. IEEE Trans. VLSI Syst. 18(7): 1118-1129 (2010)
14		Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye: Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution. IEICE Transactions 93-A(12): 2417-2423 (2010)
	2009
13		Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction. ASP-DAC 2009: 266-271
12		Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits. CICC 2009: 215-218
11		Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye: Coarse-grained dynamically reconfigurable architecture with flexible reliability. FPL 2009: 186-192
10		Koichi Hamamoto, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits. ISLPED 2009: 51-56
9		Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction. IEICE Transactions 92-A(12): 3094-3102 (2009)
8		Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability. IEICE Transactions 92-C(2): 281-285 (2009)
	2008
7		Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. ACM Great Lakes Symposium on VLSI 2008: 387-390
6		Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. ISLPED 2008: 3-8
5		Yukio Mitsuyama, Kazuma Takahashi, Rintaro Imai, Masanori Hashimoto, Takao Onoye, Isao Shirakawa: Area-Efficient Reconfigurable Architecture for Media Processing. IEICE Transactions 91-A(12): 3651-3662 (2008)
	2005
4		Yukio Mitsuyama, Motoki Kimura, Takao Onoye, Isao Shirakawa: Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems. IEICE Transactions 88-A(4): 899-906 (2005)
	2001
3		Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa: A dynamically reconfigurable hardware-based cipher chip. ASP-DAC 2001: 11-12
2		Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa: VLSI architecture of dynamically reconfigurable hardware-based cipher. ISCAS (4) 2001: 734-737
	1999
1		Koji Asari, Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, Hiroshige Hirano, Toshiyuki Honda, Tatsuo Otsuki, Takaaki Baba, Teresa H. Y. Meng: FeRAM Circuit Technology for System on a Chip. Evolvable Hardware 1999: 193-

Coauthor Index

1	Dawood Alnajiar	[11]
2	Takehiko Amaki	[16]
3	Zaldy Andales	[2] [3]
4	Koji Asari	[1]
5	Takaaki Baba	[1]
6	Hiroshi Fuketa	[6] [7] [8] [9] [12] [13] [15] [19] [23]
7	Koichi Hamamoto	[7] [8] [10]
8	Ryo Harada	[14] [17]
9	Masanori Hashimoto	[5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23]
10	Hiroshige Hirano	[1]
11	Masayuki Hiromoto	[11]
12	Toshiyuki Honda	[1]
13	Takashi Imagawa	[11]
14	Rintaro Imai	[5]
15	Toshihiro Kameda	[21]
16	Motoki Kimura	[4]
17	Younghun Ko	[11]
18	Hiroaki Konoura	[11] [18] [20] [21] [22]
19	Teresa H. Y. Meng	[1]
20	Hiroyuki Ochi	[11]
21	Takao Onoye	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23]
22	Tatsuo Otsuki	[1]
23	Isao Shirakawa	[1] [2] [3] [4] [5]
24	Kazuma Takahashi	[5]

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