 | 2009 |
| 13 |  | Tomohiko Takagi,
Kazuya Nishimachi,
Masayuki Muragishi,
Takashi Mitsuhashi,
Zengo Furukawa:
Usage Distribution Coverage: What Percentage of Expected Use Has Been Executed in Software Testing?
Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing 2009: 57-67 |
| 1998 |
| 12 |  | Takeshi Kitahara,
Fumihiro Minami,
Toshiaki Ueda,
Kimiyoshi Usami,
Seiichi Nishio,
Masami Murakata,
Takashi Mitsuhashi:
A Clock-Gating Method for Low-Power LSI Design.
ASP-DAC 1998: 307-312 |
| 1997 |
| 11 |  | Masako Murofushi,
Takashi Ishioka,
Masami Murakata,
Takashi Mitsuhashi:
Layout Driven Re-synthesis for Low Power Consumption LSIs.
DAC 1997: 666-669 |
| 1996 |
| 10 |  | Taku Uchino,
Fumihiro Minami,
Masami Murakata,
Takashi Mitsuhashi:
Switching activity analysis for sequential circuits using Boolean approximation method.
ISLPED 1996: 79-84 |
| 1995 |
| 9 |  | T. Aoki,
Masami Murakata,
Takashi Mitsuhashi,
Nobuyuki Goto:
Fanout-tree restructuring algorithm for post-placement timing optimization.
ASP-DAC 1995 |
| 8 |  | Taku Uchino,
Fumihiro Minami,
Takashi Mitsuhashi,
Nobuyuki Goto:
Switching activity analysis using Boolean approximation method.
ICCAD 1995: 20-25 |
| 7 |  | M. Tachibana,
S. Kurosawa,
R. Nojima,
Norman Kojima,
Masaaki Yamada,
Takashi Mitsuhashi,
Nobuyuki Goto:
Power and area optimization by reorganizing CMOS complex gate circuits.
ISLPD 1995: 155-160 |
| 1992 |
| 6 |  | Takashi Mitsuhashi,
Ernest S. Kuh:
Power and Ground Network Topology Optimization for Cell Based VLSIs.
DAC 1992: 524-529 |
| 1990 |
| 5 |  | Masako Murofushi,
Masaaki Yamada,
Takashi Mitsuhashi:
FOLM-Planner: A New Floorplanner with a Frame Overlapping Floorplan Model Suitable for SOG (Sea-of-Gates) Type Gate Arrays.
ICCAD 1990: 140-143 |
| 1987 |
| 4 |  | Takashi Mitsuhashi,
Kenji Yoshida:
A Resistance Calculation Algorithm and Its Application to Circuit Extraction.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(3): 337-345 (1987) |
| 1982 |
| 3 |  | Makoto Takashima,
Takashi Mitsuhashi,
Toshiaki Chiba,
Kenji Yoshida:
Programs for verifying circuit connectivity of mos/lsi mask artwork.
DAC 1982: 544-550 |
| 1980 |
| 2 |  | Takashi Mitsuhashi,
Toshiaki Chiba,
Makoto Takashima,
Kenji Yoshida:
An integrated mask artwork analysis system.
DAC 1980: 277-284 |
| 1977 |
| 1 |  | Kenji Yoshida,
Takashi Mitsuhashi,
Yasuo Nakada,
Toshiaki Chiba,
Kiyoshi Ogita,
Shinji Nakatsuka:
A layout checking system for large scale integrated circuits.
DAC 1977: 322-330 |