Enrique San Millán

	2011
17		Anna Vaskova, Celia López-Ongil, Enrique San Millán, Alejandro Jiménez-Horas, Luis Entrena: Accelerating secure circuit design with hardware implementation of Diehard Battery of tests of randomness. IOLTS 2011: 179-181
16		Honorio Martin, Enrique San Millán, Luis Entrena, Julio César Hernández Castro, Pedro Peris-Lopez: AKARI-X: A pseudorandom number generator for secure lightweight systems. IOLTS 2011: 228-233
	2010
15		Anna Vaskova, Celia López-Ongil, Alejandro Jiménez-Horas, Enrique San Millán, Luis Entrena: Robust cryptographic ciphers with on-line statistical properties validation. IOLTS 2010: 208-210
	2009
14		Alejandro Jiménez-Horas, Enrique San Millán, Celia López-Ongil, Marta Portela-García, Mario García-Valderas, Luis Entrena: Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers. IOLTS 2009: 203-205
13		Pedro Peris-Lopez, Julio C. Hernandez-Castro, Juan M. Estévez-Tapiador, Enrique San Millán, Jan C. A. van der Lubbe: Security Flaws in an Efficient Pseudo-Random Number Generator for Low-Power Environments. SEWCN 2009: 25-35
	2008
12		Enrique San Millán, Luis Entrena, José Alberto Espejo: Logic Transformations by Multiple Wire Network Addition. DSD 2008: 779-786
11		Celia López-Ongil, Alejandro Jiménez-Horas, Marta Portela-García, Mario García-Valderas, Enrique San Millán, Luis Entrena: Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard. IOLTS 2008: 167-168
	2007
10		Almudena Lindoso, Luis Entrena, Judith Liu-Jimenez, Enrique San Millán: Correlation-Based Fingerprint Matching with Orientation Field Alignment. ICB 2007: 713-721
9		Michael G. Lorenz, Luis Mengibar, Enrique San Millán, Luis Entrena: Low power data processing system with self-reconfigurable architecture. Journal of Systems Architecture 53(9): 568-576 (2007)
	2003
8		Enrique San Millán, Luis Entrena, José Alberto Espejo, Celia López: Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques. Journal of Systems Architecture 49(12-15): 529-541 (2003)
	2001
7		José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías: Functional extension of structural logic optimization techniques. ASP-DAC 2001: 467-472
6		José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías: Generalized reasoning scheme for redundancy addition and removal logic optimization. DATE 2001: 391-397
5		Enrique San Millán, Luis Entrena, José Alberto Espejo: On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. DSD 2001: 292-299
4		Enrique San Millán, Luis Entrena, José Alberto Espejo: On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits. ICCAD 2001: 91-94
3		Luis Entrena, Celia López, Emilio Olías, Enrique San Millán, José Alberto Espejo: Logic Optimization of Unidirectional Circuits with Structural Methods. IOLTW 2001: 43-47
	1999
2		Enrique San Millán, Luis Entrena, José Alberto Espejo, Silvia Chiusano, Fulvio Corno: Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization. DATE 1999: 516-520
1		José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías: Logic Restructuring for MUX-Based FPGAs. EUROMICRO 1999: 1161-

Coauthor Index

1	Julio César Hernández Castro (Julio C. Hernandez-Castro)	[13] [16]
2	Silvia Chiusano	[2]
3	Fulvio Corno	[2]
4	Luis Entrena (Luis Entrena-Arrontes)	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [14] [15] [16] [17]
5	José Alberto Espejo	[1] [2] [3] [4] [5] [6] [7] [8] [12]
6	Mario García-Valderas	[11] [14]
7	Alejandro Jiménez-Horas	[11] [14] [15] [17]
8	Almudena Lindoso	[10]
9	Judith Liu-Jimenez	[10]
10	Celia López-Ongil (Celia López)	[3] [8] [11] [14] [15] [17]
11	Michael G. Lorenz	[9]
12	Jan C. A. van der Lubbe	[13]
13	Honorio Martin	[16]
14	Luis Mengibar	[9]
15	Emilio Olías	[1] [3] [6] [7]
16	Pedro Peris-Lopez	[13] [16]
17	Marta Portela-García	[11] [14]
18	Juan E. Tapiador (Juan M. Estévez-Tapiador)	[13]
19	Anna Vaskova	[15] [17]

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