| | |
- CSB - MetaPress - Google - Bing - Yahoo
 | 2011 | |
|---|---|---|
| 7 |      | Adam Milik, Andrzej Pulka: Automatic implementation of arithmetic operation in reconfigurable logic controllers. ECCTD 2011: 721-724 |
| 2010 | ||
| 6 | | Dariusz Kania, Adam Milik: Logic synthesis based on decomposition for CPLDs. Microprocessors and Microsystems - Embedded Hardware Design 34(1): 25-38 (2010) |
| 2009 | ||
| 5 | | Andrzej Pulka, Adam Milik: Multithread RISC architecture based on programmable interleaved pipelining. ICECS 2009: 647-650 |
| 2008 | ||
| 4 | | Andrzej Pulka, Adam Milik: VEST - An Intelligent Tool for Timing SoCs Verification Using UML Timing Diagrams. FDL 2008: 118-123 |
| 2007 | ||
| 3 | | Adam Milik, Andrzej Pulka: Common HDL-Matlab Simulation Environment. FDL 2007: 68-73 |
| 2005 | ||
| 2 | | Dariusz Kania, Józef Kulisz, Adam Milik: A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs. DSD 2005: 114-121 |
| 1 | | Dariusz Kania, Adam Milik, Józef Kulisz: Decomposition of Multi-Output Functions for CPLDs. DSD 2005: 442-449 |
| 1 | Dariusz Kania | [1] [2] [6] |
| 2 | Józef Kulisz | [1] [2] |
| 3 | Andrzej Pulka | [3] [4] [5] [7] |
Colors in the list of coauthors
Last update Mon Jun 4 20:40:43 2012 CET by the DBLP Team —
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