![]() | ![]() |
| 2012 | ||
|---|---|---|
| 296 | Giovanni De Micheli: Engineering complex systems for health, security and the environment. ASP-DAC 2012: 1-6 | |
| 295 | Shashikanth Bobba, Michele De Marchi, Yusuf Leblebici, Giovanni De Micheli: Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors. DAC 2012: 42-47 | |
| 294 | Giovanni De Micheli, Cristina Boero, Camilla Baj-Rossi, Irene Taurino, Sandro Carrara: Integrated biosensors for personalized medicine. DAC 2012: 6-11 | |
| 293 | Cheng Zhang, Vasilis F. Pavlidis, Giovanni De Micheli: Voltage propagation method for 3-D power grid analysis. DATE 2012: 844-847 | |
| 292 | Hu Xu, Vasilis F. Pavlidis, Wayne Burleson, Giovanni De Micheli: The combined effect of process variations and power supply noise on clock skew and jitter. ISQED 2012: 320-327 | |
| 291 | Anish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini, Giovanni De Micheli: A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands. J. Electrical and Computer Engineering 2012: (2012) | |
| 290 | Somayyeh Rahimian, Vasilis F. Pavlidis, Giovanni De Micheli: Inter-Plane Communication Methods for 3-D ICs. J. Low Power Electronics 8(2): 170-181 (2012) | |
| 289 | Davide Sacchetto, Giovanni De Micheli, Yusuf Leblebici: Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review. Proceedings of the IEEE 100(6): 2008-2020 (2012) | |
| 2011 | ||
| 288 | Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Thomas Ernst, Olivier Faynot, David Z. Pan, Giovanni De Micheli: CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits. ASP-DAC 2011: 336-343 | |
| 287 | Wenqi You, Nicolas Widmer, Giovanni De Micheli: Personalized modeling for drug concentration prediction using Support Vector Machine. BMEI 2011: 1505-1509 | |
| 286 | Giovanni De Micheli, S. S. Ghoreishizadeh, Cristina Boero, F. Valgimigli, Sandro Carrara: An integrated platform for advanced diagnostics. DATE 2011: 1454-1459 | |
| 285 | Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli: Analytical heat transfer model for thermal through-silicon vias. DATE 2011: 395-400 | |
| 284 | Giovanni De Micheli: Logic synthesis and physical design: Quo vadis? DATE 2011: 50 | |
| 283 | Davide Sacchetto, Michele De Marchi, Giovanni De Micheli, Yusuf Leblebici: Alternative design methodologies for the next generation logic switch. ICCAD 2011: 231-234 | |
| 282 | Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli: Skew variability in 3-D ICs with multiple clock domains. ISCAS 2011: 2221-2224 | |
| 281 | Francesco Zanini, David Atienza, Luca Benini, Giovanni De Micheli: Thermal-aware system-level modeling and management for Multi-Processor Systems-on-Chip. ISCAS 2011: 2481-2484 | |
| 280 | Daniela De Venuto, Sandro Carrara, Andrea Cavallini, Giovanni De Micheli: pH sensing with temperature compensation in a Molecular Biosensor for drugs detection. ISQED 2011: 326-331 | |
| 279 | Anish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini, Giovanni De Micheli: A Simulation Based Buffer Sizing Algorithm for Network on Chips. ISVLSI 2011: 206-211 | |
| 278 | Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli: A DRAM Centric NoC Architecture and Topology Design Approach. ISVLSI 2011: 54-59 | |
| 277 | Somayyeh Rahimian, Vasilis F. Pavlidis, Giovanni De Micheli: Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits. PATMOS 2011: 267-277 | |
| 276 | Francesco Zanini, David Atienza, Giovanni De Micheli: Convex-Based Thermal Management for 3D MPSoCs Using DVFS and Variable-Flow Liquid Cooling. PATMOS 2011: 341-350 | |
| 275 | Jaume Joven, Per Strict, David Castells-Rufas, Akash Bagdia, Giovanni De Micheli, Jordi Carrabina: HW-SW implementation of a decoupled FPU for ARM-based Cortex-M1 SoCs in FPGAs. SIES 2011: 1-8 | |
| 274 | M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli: An Efficient Gate Library for Ambipolar CNTFET Logic. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 242-255 (2011) | |
| 2010 | ||
| 273 | Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Vasilis F. Pavlidis, Giovanni De Micheli: Performance analysis of 3-D monolithic integrated circuits. 3DIC 2010: 1-4 | |
| 272 | Francesco Zanini, David Atienza, Giovanni De Micheli, Stephen P. Boyd: Online convex optimization-based algorithm for thermal management of MPSoCs. ACM Great Lakes Symposium on VLSI 2010: 203-208 | |
| 271 | Srinivasan Murali, Luca Benini, Giovanni De Micheli: Design of networks on chips for 3D ICs. ASP-DAC 2010: 167-168 | |
| 270 | Michele Lombardi, Luca Benini, Abhishek Garg, Giovanni De Micheli: Methods for Designing Reliable Probe Arrays. BIBE 2010: 306-307 | |
| 269 | Jaume Joven, Andrea Marongiu, Federico Angiolini, Luca Benini, Giovanni De Micheli: Exploring programming model-driven QoS support for NoC-based platforms. CODES+ISSS 2010: 65-74 | |
| 268 | Giovanni De Micheli, Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Federico Angiolini, Antonio Pullini: Networks on Chips: from research to products. DAC 2010: 300-305 | |
| 267 | Jie Zhang, Shashikanth Bobba, Nishant Patil, Albert Lin, H.-S. Philip Wong, Giovanni De Micheli, Subhasish Mitra: Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement. DAC 2010: 889-892 | |
| 266 | Marco Casale-Rossi, Giovanni De Micheli, Antun Domic, Enrico Macii, Piero Perlo, Andreas Wild, Roberto Zafalon: Panel: First commandment at least, do nothing well! DATE 2010: 1377 | |
| 265 | Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli: A method to remove deadlocks in Networks-on-Chips with Wormhole flow control. DATE 2010: 1625-1628 | |
| 264 | M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli: Power consumption of logic circuits in ambipolar carbon nanotube technology. DATE 2010: 303-306 | |
| 263 | Ioannis Tsioutsios, Vasilis F. Pavlidis, Giovanni De Micheli: Physical design tradeoffs in power distribution networks for 3-D ICs. ICECS 2010: 430-433 | |
| 262 | Michele De Marchi, Shashikanth Bobba, M. Haykel Ben Jamaa, Giovanni De Micheli: Synthesis of regular computational fabrics with ambipolar CNTFET technology. ICECS 2010: 70-73 | |
| 261 | Francesco Zanini, David Atienza, Colin N. Jones, Giovanni De Micheli: Temperature sensor placement in thermal management systems for MPSoCs. ISCAS 2010: 1065-1068 | |
| 260 | Nikolaos Archontas, Julius Georgiou, M. Haykel Ben Jamaa, Sandro Carrara, Giovanni De Micheli: Characterization of memristive Poly-Si Nanowires via empirical physical modelling. ISCAS 2010: 1675-1678 | |
| 259 | Shashikanth Bobba, Sandro Carrara, Giovanni De Micheli: Design of a CNFET array for sensing and control in P450 based biochips for multiple drug detection. ISCAS 2010: 1711-1714 | |
| 258 | Davide Sacchetto, M. Haykel Ben Jamaa, Giovanni De Micheli, Yusuf Leblebici: Design aspects of carry lookahead adders with vertically-stacked nanowire transistors. ISCAS 2010: 1715-1718 | |
| 257 | Francesco Zanini, Colin N. Jones, David Atienza, Giovanni De Micheli: Multicore thermal management using approximate explicit model predictive control. ISCAS 2010: 3321-3324 | |
| 256 | Davide Sacchetto, M. Haykel Ben Jamaa, Sandro Carrara, Giovanni De Micheli, Yusuf Leblebici: Memristive devices fabricated with silicon nanowire schottky barrier transistors. ISCAS 2010: 9-12 | |
| 255 | Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli: Process-induced skew variation for scaled 2-D and 3-D ICs. SLIP 2010: 17-24 | |
| 254 | Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli: SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips. IEEE Trans. on CAD of Integrated Circuits and Systems 29(12): 1987-2000 (2010) | |
| 253 | Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli: Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands. IEEE Trans. on Circuits and Systems 57-II(5): 364-368 (2010) | |
| 252 | Sandro Carrara, Andrea Cavallini, Yusuf Leblebici, Giovanni De Micheli, Vijayender Bhalla, Francesco Valle, Bruno Samorì, Luca Benini, Bruno Riccò, Inger Vikholm-Lundin, Tony Munter: Capacitance DNA bio-chips improved by new probe immobilization strategies. Microelectronics Journal 41(11): 711-717 (2010) | |
| 2009 | ||
| 251 | Vasilis F. Pavlidis, Giovanni De Micheli: Power distribution paths in 3-D ICS. ACM Great Lakes Symposium on VLSI 2009: 263-268 | |
| 250 | Srinivasan Murali, Ciprian Seiculescu, Luca Benini, Giovanni De Micheli: Synthesis of networks on chips for 3D systems on chips. ASP-DAC 2009: 242-247 | |
| 249 | Francesco Zanini, David Atienza, Giovanni De Micheli: A control theory approach for thermal balancing of MPSoC. ASP-DAC 2009: 37-42 | |
| 248 | M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli: A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories. ASP-DAC 2009: 835-840 | |
| 247 | Francisco J. Rincón, Laura Gutiérrez, Mónica Jiménez, Víctor Díaz, Nadia Khaled, David Atienza, Marcos Sanchez-Elez, Joaquín Recas, Giovanni De Micheli: Implementation of an Automated ECG-based Diagnosis Algorithm for a Wireless Body Sensor Plataform. BIODEVICES 2009: 88-96 | |
| 246 | M. Haykel Ben Jamaa, Gianfranco Cerofolini, Yusuf Leblebici, Giovanni De Micheli: Complete nanowire crossbar framework optimized for the multi-spacer patterning technique. CASES 2009: 11-16 | |
| 245 | M. Haykel Ben Jamaa, Yusuf Leblebici, Giovanni De Micheli: Decoding nanowire arrays fabricated with the multi-spacer patterning technique. DAC 2009: 77-82 | |
| 244 | Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli: NoC topology synthesis for supporting shutdown of voltage islands in SoCs. DAC 2009: 822-825 | |
| 243 | Marco Casale-Rossi, Giovanni De Micheli: Panel session - Consolidation, a modern "Moor of Venice" tale. DATE 2009: 141 | |
| 242 | Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Giovanni De Micheli, Enrico Macii: Physically clustered forward body biasing for variability compensation in nanometer CMOS design. DATE 2009: 154-159 | |
| 241 | Shashikanth Bobba, Jie Zhang, Antonio Pullini, David Atienza, Giovanni De Micheli: Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis. DATE 2009: 616-621 | |
| 240 | M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli: Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis. DATE 2009: 622-627 | |
| 239 | Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli: SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips. DATE 2009: 9-14 | |
| 238 | Eugène David Ngangue Ndih, Nadia Khaled, Giovanni De Micheli: An Analytical Model for the Contention Access Period of the Slotted IEEE 802.15.4 with Service Differentiation. ICC 2009: 1-6 | |
| 237 | Dara Rahmati, Srinivasan Murali, Luca Benini, Federico Angiolini, Giovanni De Micheli, Hamid Sarbazi-Azad: A method for calculating hard QoS guarantees for Networks-on-Chip. ICCAD 2009: 579-586 | |
| 236 | Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli: Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits. NanoNet 2009: 141-150 | |
| 235 | Sandro Carrara, Cristina Boero, Giovanni De Micheli: Quantum Dots and Wires to Improve Enzymes-Based Electrochemical Bio-sensing. NanoNet 2009: 189-199 | |
| 234 | Abhishek Garg, Kartik Mohanram, Alessandro Di Cara, Giovanni De Micheli, Ioannis Xenarios: Modeling stochasticity and robustness in gene regulatory networks. Bioinformatics 25(12): (2009) | |
| 233 | Fabrizio Mulas, David Atienza, Andrea Acquaviva, Salvatore Carta, Luca Benini, Giovanni De Micheli: Thermal Balancing Policy for Multiprocessor Stream Computing Platforms. IEEE Trans. on CAD of Integrated Circuits and Systems 28(12): 1870-1882 (2009) | |
| 232 | Giovanni De Micheli: An Outlook on Design Technologies for Future Integrated Systems. IEEE Trans. on CAD of Integrated Circuits and Systems 28(6): 777-790 (2009) | |
| 231 | Almir Mutapcic, Stephen P. Boyd, Srinivasan Murali, David Atienza, Giovanni De Micheli, Rajesh Gupta: Processor Speed Control With Thermal Constraints. IEEE Trans. on Circuits and Systems 56-I(9): 1994-2008 (2009) | |
| 2008 | ||
| 230 | David Atienza, Giovanni De Micheli, Luca Benini, José L. Ayala, Pablo Garcia Del Valle, Michael DeBole, Vijaykrishnan Narayanan: Reliability-aware design for nanometer-scale devices. ASP-DAC 2008: 549-554 | |
| 229 | M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli: Programmable logic circuits based on ambipolar CNFET. DAC 2008: 339-340 | |
| 228 | Giovanni De Micheli: Designing Micro/Nano Systems for a Safer and Healthier Tomorrow. DATE 2008: 1 | |
| 227 | Francisco J. Rincón, Michele Paselli, Joaquín Recas, Qin Zhao, Marcos Sanchez-Elez, David Atienza, Julien Penders, Giovanni De Micheli: OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks. DATE 2008: 1027-1032 | |
| 226 | Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen P. Boyd, Luca Benini, Giovanni De Micheli: Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization. DATE 2008: 110-115 | |
| 225 | Fabrizio Mulas, Michele Pittau, Marco Buttu, Salvatore Carta, Andrea Acquaviva, Luca Benini, David Atienza, Giovanni De Micheli: Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures. DATE 2008: 734-739 | |
| 224 | Giovanni De Micheli: System-level design technologies for heterogeneous distributed systems. SBCCI 2008: 5 | |
| 223 | Abhishek Garg, Alessandro Di Cara, Ioannis Xenarios, Luis Mendoza, Giovanni De Micheli: Synchronous versus asynchronous modeling of gene regulatory networks. Bioinformatics 24(17): 1917-1925 (2008) | |
| 222 | Elisa Ficarra, Giovanni De Micheli, Sungroh Yoon, Luca Benini, Enrico Macii: Joint co-clustering: Co-clustering of genomic and clinical bioimaging data. Computers & Mathematics with Applications 55(5): 938-949 (2008) | |
| 221 | Giovanni De Micheli: Designing Micro- and Nanosystems for a Safer and Healthier Tomorrow. IEEE Design & Test of Computers 25(5): 488-494 (2008) | |
| 220 | M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli: Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories. IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 2053-2067 (2008) | |
| 219 | Terry Tao Ye, Giovanni De Micheli: On-chip implementation of multiprocessor networks and switch fabrics. IJES 3(4): 209-218 (2008) | |
| 218 | David Atienza, Praveen Raghavan, José Luis Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo: Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures. Integration 41(1): 38-48 (2008) | |
| 217 | David Atienza, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Luca Benini, Giovanni De Micheli: Network-on-Chip design and synthesis outlook. Integration 41(3): 340-359 (2008) | |
| 2007 | ||
| 216 | Salvatore Carta, Andrea Acquaviva, Pablo Garcia Del Valle, David Atienza, Giovanni De Micheli, Fernando Rincón, Luca Benini, Jose Manuel Mendias: Multi-processor operating system emulation framework with thermal feedback for systems-on-chip. ACM Great Lakes Symposium on VLSI 2007: 311-316 | |
| 215 | Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen P. Boyd, Giovanni De Micheli: Temperature-aware processor frequency assignment for MPSoCs using convex optimization. CODES+ISSS 2007: 111-116 | |
| 214 | Federico Angiolini, M. Haykel Ben Jamaa, David Atienza, Luca Benini, Giovanni De Micheli: Interactive presentation: Improving the fault tolerance of nanometric PLA designs. DATE 2007: 570-575 | |
| 213 | M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli: Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays. ICCAD 2007: 765-772 | |
| 212 | Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo: Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors. ISCAS 2007: 121-124 | |
| 211 | Giovanni De Micheli: Design Technologies for Networks on Chips. NOCS 2007: 149 | |
| 210 | Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini: NoC Design and Implementation in 65nm Technology. NOCS 2007: 273-282 | |
| 209 | Abhishek Garg, Ioannis Xenarios, Luis Mendoza, Giovanni De Micheli: An Efficient Method for Dynamic Analysis of Gene Regulatory Networks and in silico Gene Perturbation Experiments. RECOMB 2007: 62-76 | |
| 208 | Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli: Early wire characterization for predictable network-on-chip global interconnects. SLIP 2007: 57-64 | |
| 207 | David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida: HW-SW emulation framework for temperature-aware design in MPSoCs. ACM Trans. Design Autom. Electr. Syst. 12(3): (2007) | |
| 206 | Sungroh Yoon, Jessica C. Ebert, Eui-Young Chung, Giovanni De Micheli, Russ B. Altman: Clustering protein environments for function prediction: finding PROSITE motifs in 3D. BMC Bioinformatics 8(S-4): (2007) | |
| 205 | Alessandro Di Cara, Abhishek Garg, Giovanni De Micheli, Ioannis Xenarios, Luis Mendoza: Dynamic simulation of regulatory networks using SQUAD. BMC Bioinformatics 8: (2007) | |
| 204 | Srinivasan Murali, Giovanni De Micheli: An Application-Specific Design Methodology for STbus Crossbar Generation CoRR abs/0710.4671: (2007) | |
| 203 | Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini: Bringing NoCs to 65 nm. IEEE Micro 27(5): 75-85 (2007) | |
| 202 | Tajana Simunic Rosing, Kresimir Mihic, Giovanni De Micheli: Power and Reliability Management of SoCs. IEEE Trans. VLSI Syst. 15(4): 391-403 (2007) | |
| 201 | Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo: Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. IEEE Trans. VLSI Syst. 15(8): 869-880 (2007) | |
| 200 | Srinivasan Murali, Luca Benini, Giovanni De Micheli: An Application-Specific Design Methodology for On-Chip Crossbar Generation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1283-1296 (2007) | |
| 199 | Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini, Giovanni De Micheli: Timing-Error-Tolerant Network-on-Chip Design Methodology. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1297-1310 (2007) | |
| 198 | Sungroh Yoon, Luca Benini, Giovanni De Micheli: Co-clustering: A Versatile Tool for Data Analysis in Biomedical Informatics. IEEE Transactions on Information Technology in Biomedicine 11(4): 493-494 (2007) | |
| 197 | Alex E. Susu, Michele Magno, Andrea Acquaviva, David Atienza, Giovanni De Micheli: Reconfiguration Strategies for Environmentally Powered Devices: Theoretical Analysis and Experimental Validation. T. HiPEAC 1: 341-360 (2007) | |
| 196 | Srinivasan Murali, David Atienza, Luca Benini, Giovanni De Micheli: A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees. VLSI Design 2007: (2007) | |
| 2006 | ||
| 195 | Ayse Kivilcim Coskun, Tajana Simunic Rosing, Yusuf Leblebici, Giovanni De Micheli: A simulation methodology for reliability analysis in multi-core SoCs. ACM Great Lakes Symposium on VLSI 2006: 95-99 | |
| 194 | Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli: Mapping and configuration methods for multi-use-case networks on chips. ASP-DAC 2006: 146-151 | |
| 193 | Elisa Ficarra, Enrico Macii, Giovanni De Micheli, Luca Benini: Computer-Aided Evaluation of Protein Expression in Pathological Tissue Images. CBMS 2006: 413-418 | |
| 192 | Martijn Coenen, Srinivasan Murali, Andrei Radulescu, Kees Goossens, Giovanni De Micheli: A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control. CODES+ISSS 2006: 130-135 | |
| 191 | Igino Folcarelli, Alex E. Susu, Ties Kluter, Giovanni De Micheli, Andrea Acquaviva: An opportunistic reconfiguration strategy for environmentally powered devices. Conf. Computing Frontiers 2006: 171-176 | |
| 190 | David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias: A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip. DAC 2006: 618-623 | |
| 189 | Srinivasan Murali, David Atienza, Luca Benini, Giovanni De Micheli: A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip. DAC 2006: 845-848 | |
| 188 | Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli: A methodology for mapping multiple use-cases onto networks on chips. DATE 2006: 118-123 | |
| 187 | Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo: Designing application-specific networks on chips with floorplan information. ICCAD 2006: 355-362 | |
| 186 | Federico Angiolini, David Atienza, Srinivasan Murali, Luca Benini, Giovanni De Micheli: Reliability Support for On-Chip Memories Using Networks-on-Chip. ICCD 2006 | |
| 185 | Christine Nardini, Daniele Masotti, Sungroh Yoon, Enrico Macii, Michael D. Kuo, Giovanni De Micheli, Luca Benini: Mining Gene Sets for Measuring Similarities. ISCC 2006: 227-232 | |
| 184 | David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo: Compiler-Driven Leakage Energy Reduction in Banked Register Files. PATMOS 2006: 107-116 | |
| 183 | Giovanni De Micheli: Nanoelectronics: Challenges and Opportunities. PATMOS 2006: 658 | |
| 182 | Pablo Garcia Del Valle, David Atienza, Ivan Magan, Javier Garcia Flores, Esther Andres Perez, Jose Manuel Mendias, Luca Benini, Giovanni De Micheli: A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework. VLSI-SoC 2006: 140-145 | |
| 181 | Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo: Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips. VLSI-SoC 2006: 158-163 | |
| 180 | Sungroh Yoon, Luca Benini, Giovanni De Micheli: A Pattern-Mining Method for High-Throughput Lab-on-a-Chip Data Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 25(2): 358-377 (2006) | |
| 179 | Ayse Kivilcim Coskun, Tajana Simunic, Kresimir Mihic, Giovanni De Micheli, Yusuf Leblebici: Analysis and Optimization of MPSoC Reliability. J. Low Power Electronics 2(1): 56-69 (2006) | |
| 2005 | ||
| 178 | Srinivasan Murali, Luca Benini, Giovanni De Micheli: Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees. ASP-DAC 2005: 27-32 | |
| 177 | Rutuparna Tamhankar, Srinivasan Murali, Giovanni De Micheli: Performance driven reliable link design for networks on chips. ASP-DAC 2005: 749-754 | |
| 176 | Srinivasan Murali, Giovanni De Micheli: An Application-Specific Design Methodology for STbus Crossbar Generation. DATE 2005: 1176-1181 | |
| 175 | Stergios Stergiou, Federico Angiolini, Salvatore Carta, Luigi Raffo, Davide Bertozzi, Giovanni De Micheli: ast pipes Lite: A Synthesis Oriented Design Library For Networks on Chips. DATE 2005: 1188-1193 | |
| 174 | Nicolas Genko, David Atienza, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida, Francky Catthoor: A Complete Network-On-Chip Emulation Framework. DATE 2005: 246-251 | |
| 173 | Sungroh Yoon, Giovanni De Micheli: Prediction of regulatory modules comprising microRNAs and target genes. ECCB/JBI 2005: 100 | |
| 172 | Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli: Self-calibrating networks-on-chip. ISCAS (3) 2005: 2361-2364 | |
| 171 | Nicolas Genko, David Atienza, Giovanni De Micheli, Luca Benini, Jose Manuel Mendias, Román Hermida, Francky Catthoor: A novel approach for network on chip emulation. ISCAS (3) 2005: 2365-2368 | |
| 170 | Nicolas Genko, David Atienza, Giovanni De Micheli: Exploration and Tuning of Custom NoC Topologies Using an FPGA-Based Framework. PARCO 2005: 753-760 | |
| 169 | Tajana Simunic, Kresimir Mihic, Giovanni De Micheli: Optimization of Reliability and Power Consumption in Systems on a Chip. PATMOS 2005: 237-246 | |
| 168 | Davide Bertozzi, Luca Benini, Giovanni De Micheli: Network On-Chip Design for Gigascale Systems-on-Chip. The Industrial Information Technology Handbook 2005: 0- | |
| 167 | Giovanni De Micheli, Al Dunlop: IEEE Council for Electronic Design Automation: A new beginning. IEEE Design & Test of Computers 22(4): 293-294 (2005) | |
| 166 | André Ivanov, Giovanni De Micheli: Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research. IEEE Design & Test of Computers 22(5): 399-403 (2005) | |
| 165 | Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, Giovanni De Micheli: Design, Synthesis, and Test of Networks on Chips. IEEE Design & Test of Computers 22(5): 404-413 (2005) | |
| 164 | Srinivasan Murali, Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin, Luca Benini, Giovanni De Micheli: Analysis of Error Recovery Schemes for Networks on Chips. IEEE Design & Test of Computers 22(5): 434-442 (2005) | |
| 163 | Davide Bertozzi, Antoine Jalabert, Srinivasan Murali, Rutuparna Tamhankar, Stergios Stergiou, Luca Benini, Giovanni De Micheli: NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip. IEEE Trans. Parallel Distrib. Syst. 16(2): 113-129 (2005) | |
| 162 | Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli: A robust self-calibrating transmission scheme for on-chip networks. IEEE Trans. VLSI Syst. 13(1): 126-139 (2005) | |
| 161 | Davide Bertozzi, Luca Benini, Giovanni De Micheli: Error control schemes for on-chip communication links: the energy-reliability tradeoff. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 818-831 (2005) | |
| 160 | Sungroh Yoon, Christine Nardini, Luca Benini, Giovanni De Micheli: Discovering Coherent Biclusters from Gene Expression Data Using Zero-Suppressed Binary Decision Diagrams. IEEE/ACM Trans. Comput. Biology Bioinform. 2(4): 339-354 (2005) | |
| 2004 | ||
| 159 | Sungroh Yoon, Christine Nardini, Luca Benini, Giovanni De Micheli: Enhanced pClustering and Its Applications to Gene Expression Data. BIBE 2004: 275-282 | |
| 158 | Giovanni De Micheli: Reliable communication in systems on chips. DAC 2004: 77 | |
| 157 | Srinivasan Murali, Giovanni De Micheli: SUNMAP: a tool for automatic topology selection and generation for NoCs. DAC 2004: 914-919 | |
| 156 | Antoine Jalabert, Srinivasan Murali, Luca Benini, Giovanni De Micheli: ×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip. DATE 2004: 884-889 | |
| 155 | Srinivasan Murali, Giovanni De Micheli: Bandwidth-Constrained Mapping of Cores onto NoC Architectures. DATE 2004: 896-903 | |
| 154 | Kresimir Mihic, Tajana Simunic, Giovanni De Micheli: Reliability and Power Management of Integrated Systems. DSD 2004: 5-11 | |
| 153 | Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli: On-Chip Self-Calibrating Communication Techniques Robust to Electrical Parameter Variations. IEEE Design & Test of Computers 21(6): 524-535 (2004) | |
| 152 | Terry Tao Ye, Luca Benini, Giovanni De Micheli: Packetization and routing analysis of on-chip multiprocessor networks. Journal of Systems Architecture 50(2-3): 81-104 (2004) | |
| 2003 | ||
| 151 | Armita Peymandoust, Laura Pozzi, Paolo Ienne, Giovanni De Micheli: Automatic Instruction Set Extension and Utilization for Embedded Processors. ASAP 2003: 108- | |
| 150 | Terry Tao Ye, Giovanni De Micheli: Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics. ASAP 2003: 97-107 | |
| 149 | Terry Tao Ye, Luca Benini, Giovanni De Micheli: Packetized On-Chip Interconnect Communication Analysis for MPSoC. DATE 2003: 10344-10349 | |
| 148 | Giovanni De Micheli: Robust System Design with Uncertain Information. MEMOCODE 2003: 283- | |
| 147 | Wajahat Qadeer, Tajana Simunic Rosing, John Ankcorn, Venky Krishnan, Giovanni De Micheli: Heterogeneous Wireless Network Management. PACS 2003: 86-100 | |
| 146 | Giovanni De Micheli: CASS Brings Publishing to Its DAC Partnership. IEEE Design & Test of Computers 20(3): 101-102 (2003) | |
| 145 | Armita Peymandoust, Tajana Simunic, Giovanni De Micheli: Complex instruction and software library mapping for embedded software using symbolic algebra. IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 964-975 (2003) | |
| 144 | Armita Peymandoust, Giovanni De Micheli: Application of symbolic computer algebra in high-level data-flow synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1154-1165 (2003) | |
| 2002 | ||
| 143 | Giovanni De Micheli, Rolf Ernst, Wayne Wolf: Readings in hardware / software co-design. Morgan Kaufmann 2002: I-XIV, 1-697 | |
| 142 | Armita Peymandoust, Giovanni De Micheli, Tajana Simunic: Complex library mapping for embedded software using symbolic algebra. DAC 2002: 325-330 | |
| 141 | Terry Tao Ye, Giovanni De Micheli, Luca Benini: Analysis of power consumption on switch fabrics in network routers. DAC 2002: 524-529 | |
| 140 | Davide Bertozzi, Luca Benini, Giovanni De Micheli: Low Power Error Resilient Encoding for On-Chip Data Buses. DATE 2002: 102-109 | |
| 139 | Armita Peymandoust, Tajana Simunic, Giovanni De Micheli: Low Power Embedded Software Optimization Using Symbolic Algebra. DATE 2002: 1052-1058 | |
| 138 | Giovanni De Micheli, Luca Benini: Networks on Chip: A New Paradigm for Systems on Chip Design. DATE 2002: 418-419 | |
| 137 | Terry Tao Ye, Samit Chaudhuri, F. Huang, Hamid Savoj, Giovanni De Micheli: Physical synthesis for ASIC datapath circuits. ISCAS (3) 2002: 365-368 | |
| 136 | Eui-Young Chung, Giovanni De Micheli, Luca Benini: Contents provider-assisted dynamic voltage scaling for low energy multimedia applications. ISLPED 2002: 42-47 | |
| 135 | Paolo Ienne, Patrick Thiran, Giovanni De Micheli, Frederic Worm: An Adaptive Low-Power Transmission Scheme for On-Chip Networks. ISSS 2002: 92-100 | |
| 134 | Luca Benini, Giovanni De Micheli: Networks on Chips: A New SoC Paradigm. IEEE Computer 35(1): 70-78 (2002) | |
| 133 | Eui-Young Chung, Luca Benini, Alessandro Bogliolo, Yung-Hsiang Lu, Giovanni De Micheli: Dynamic Power Management for Nonstationary Service Requests. IEEE Trans. Computers 51(11): 1345-1361 (2002) | |
| 132 | Yung-Hsiang Lu, Luca Benini, Giovanni De Micheli: Power-aware operating systems for interactive systems. IEEE Trans. VLSI Syst. 10(2): 119-134 (2002) | |
| 131 | Yung-Hsiang Lu, Luca Benini, Giovanni De Micheli: Dynamic frequency scaling with buffer insertion for mixed workloads. IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1284-1305 (2002) | |
| 130 | Eui-Young Chung, Luca Benini, Giovanni De Micheli, Gabriele Luculli, Marco Carilli: Value-sensitive automatic code specialization for embedded software. IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1051-1067 (2002) | |
| 2001 | ||
| 129 | Armita Peymandoust, Giovanni De Micheli: Using Symbolic Algebra in Algorithmic Level DSP Synthesis. DAC 2001: 277-282 | |
| 128 | Tajana Simunic, Luca Benini, Andrea Acquaviva, Peter W. Glynn, Giovanni De Micheli: Dynamic Voltage Scaling and Power Management for Portable Systems. DAC 2001: 524-529 | |
| 127 | G. Martin, Ralf Seepold, Ting Zhang, Luca Benini, Giovanni De Micheli: Component selection and matching for IP-based design. DATE 2001: 40-46 | |
| 126 | Armita Peymandoust, Giovanni De Micheli: Symbolic Algebra and Timing Driven Data-flow Synthesis. ICCAD 2001: 300-305 | |
| 125 | Eui-Young Chung, Luca Benini, Giovanni De Micheli: Automatic source code specialization for energy reduction. ISLPED 2001: 80-83 | |
| 124 | Preeti Ranjan Panda, Luc Séméria, Giovanni De Micheli: Cache-efficient memory layout of aggregate data structures. ISSS 2001: 101-106 | |
| 123 | Eui-Young Chung, Luca Benini, Giovanni De Micheli: Source code transformation based on software cost analysis. ISSS 2001: 153-158 | |
| 122 | Luca Benini, Giovanni De Micheli: Powering networks on chips. ISSS 2001: 33-38 | |
| 121 | Yung-Hsiang Lu, Giovanni De Micheli: Comparing System-Level Power Management Policies. IEEE Design & Test of Computers 18(2): 10-19 (2001) | |
| 120 | Tajana Simunic, Luca Benini, Giovanni De Micheli: Energy-efficient design of battery-powered embedded systems. IEEE Trans. VLSI Syst. 9(1): 15-28 (2001) | |
| 119 | Luc Séméria, Koichi Sato, Giovanni De Micheli: Synthesis of hardware models in C with pointers and complex data structures. IEEE Trans. VLSI Syst. 9(6): 743-756 (2001) | |
| 118 | James Smith, Giovanni De Micheli: Polynomial circuit models for component matching in high-level synthesis. IEEE Trans. VLSI Syst. 9(6): 783-800 (2001) | |
| 117 | Luc Séméria, Giovanni De Micheli: Resolution, optimization, and encoding of pointer variables for thebehavioral synthesis from C. IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 213-233 (2001) | |
| 116 | Tajana Simunic, Luca Benini, Peter W. Glynn, Giovanni De Micheli: Event-driven power management. IEEE Trans. on CAD of Integrated Circuits and Systems 20(7): 840-857 (2001) | |
| 115 | Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino: Synthesis of power-managed sequential components based oncomputational kernel extraction. IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1118-1131 (2001) | |
| 2000 | ||
| 114 | Giovanni De Micheli: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000. ACM 2000 | |
| 113 | Yung-Hsiang Lu, Luca Benini, Giovanni De Micheli: Low-power task scheduling for multiple devices. CODES 2000: 39-43 | |
| 112 | Yung-Hsiang Lu, Eui-Young Chung, Tajana Simunic, Giovanni De Micheli, Luca Benini: Quantitative Comparison of Power Management Algorithms. DATE 2000: 20-26 | |
| 111 | Luc Séméria, Koichi Sato, Giovanni De Micheli: Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from C. DATE 2000: 312-319 | |
| 110 | Tajana Simunic, Luca Benini, Peter W. Glynn, Giovanni De Micheli: Dynamic Power Management of Laptop Hard Disk. DATE 2000: 736 | |
| 109 | Terry Tao Ye, Giovanni De Micheli: Data Path Placement with Regularity. ICCAD 2000: 264-270 | |
| 108 | Giovanni De Micheli, Tony Correale, Pietro Erratico, Srini Raghvendra, Hugo De Man, Jerry Frankil, Vivek Tiwari: Do our low-power tools have enough horse power? (panel session) (title only). ISLPED 2000: 149 | |
| 107 | Yung-Hsiang Lu, Luca Benini, Giovanni De Micheli: Operating-system directed power reduction. ISLPED 2000: 37-42 | |
| 106 | Tajana Simunic, Haris Vikalo, Peter W. Glynn, Giovanni De Micheli: Energy efficient design of portable wireless systems. ISLPED 2000: 49-54 | |
| 105 | Yung-Hsiang Lu, Giovanni De Micheli, Luca Benini: Requester-Aware Power Reduction. ISSS 2000: 18-24 | |
| 104 | Tajana Simunic, Giovanni De Micheli, Luca Benini, Mat Hans: Source Code Optimization and Profiling of Energy Consumption in Embedded Systems. ISSS 2000: 193-199 | |
| 103 | Tajana Simunic, Luca Benini, Peter W. Glynn, Giovanni De Micheli: Dynamic power management for portable systems. MOBICOM 2000: 11-19 | |
| 102 | Luca Benini, Giovanni De Micheli: System-level power optimization: techniques and tools. ACM Trans. Design Autom. Electr. Syst. 5(2): 115-192 (2000) | |
| 101 | Luca Benini, Giovanni De Micheli: Synthesis of low-power selectively-clocked systems from high-level specification. ACM Trans. Design Autom. Electr. Syst. 5(3): 311-321 (2000) | |
| 100 | Alessandro Bogliolo, Luca Benini, Giovanni De Micheli: Regression-based RTL power modeling. ACM Trans. Design Autom. Electr. Syst. 5(3): 337-372 (2000) | |
| 99 | Vincent John Mooney III, Giovanni De Micheli: Hardware/Software Co-Design of Run-Time Schedulers for Real-Time Systems. Design Autom. for Emb. Sys. 6(1): 89-144 (2000) | |
| 98 | Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi: Glitch power minimization by selective gate freezing. IEEE Trans. VLSI Syst. 8(3): 287-298 (2000) | |
| 97 | Luca Benini, Alessandro Bogliolo, Giovanni De Micheli: A survey of design techniques for system-level dynamic power management. IEEE Trans. VLSI Syst. 8(3): 299-316 (2000) | |
| 96 | Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi: A multilevel engine for fast power simulation of realistic inputstreams. IEEE Trans. on CAD of Integrated Circuits and Systems 19(4): 459-472 (2000) | |
| 1999 | ||
| 95 | Yung-Hsiang Lu, Tajana Simunic, Giovanni De Micheli: Software controlled power management. CODES 1999: 157-161 | |
| 94 | Luca Benini, Giovanni De Micheli, Enrico Macii, Giuseppe Odasso, Massimo Poncino: Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms. DAC 1999: 247-252 | |
| 93 | Tajana Simunic, Luca Benini, Giovanni De Micheli: Cycle-Accurate Simulation of Energy Consumption in Embedded Systems. DAC 1999: 867-872 | |
| 92 | Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi: Glitch Power Minimization by Gate Freezing. DATE 1999: 163-167 | |
| 91 | James Smith, Giovanni De Micheli: Polynomial Methods for Allocating Complex Components. DATE 1999: 217-222 | |
| 90 | Giovanni De Micheli: Hardware Synthesis from C/C++ Models. DATE 1999: 382-383 | |
| 89 | Eui-Young Chung, Luca Benini, Alessandro Bogliolo, Giovanni De Micheli: Dynamic Power Management for non-stationary service requests. DATE 1999: 77-81 | |
| 88 | Yung-Hsiang Lu, Giovanni De Micheli: Adaptive Hard Disk Power Management on Personal Computers. Great Lakes Symposium on VLSI 1999: 50- | |
| 87 | Eui-Young Chung, Luca Benini, Giovanni De Micheli: Dynamic power management using adaptive learning tree. ICCAD 1999: 274-279 | |
| 86 | Alessandro Bogliolo, Luca Benini, Bruno Riccò, Giovanni De Micheli: Efficient switching activity computation during high-level synthesis of control-dominated designs. ISLPED 1999: 127-132 | |
| 85 | Tajana Simunic, Luca Benini, Giovanni De Micheli: Energy-efficient design of battery-powered embedded systems. ISLPED 1999: 212-217 | |
| 84 | Luca Benini, Giovanni De Micheli: System-level power optimization: techniques and tools. ISLPED 1999: 288-293 | |
| 83 | Tajana Simunic, Giovanni De Micheli, Luca Benini: Event-Driven Power Management of Portable Systems. ISSS 1999: 18-23 | |
| 82 | Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi: Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers. ACM Trans. Design Autom. Electr. Syst. 4(4): 351-375 (1999) | |
| 81 | Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino: Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting. IEEE Trans. Computers 48(8): 769-779 (1999) | |
| 80 | Luca Benini, Alessandro Bogliolo, Giuseppe A. Paleologo, Giovanni De Micheli: Policy optimization for dynamic power management. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 813-833 (1999) | |
| 1998 | ||
| 79 | Luca Benini, Giovanni De Micheli: Dynamic power management - design techniques and CAD tools. Kluwer 1998: I-XIII, 1-231 | |
| 78 | James Smith, Giovanni De Micheli: Automated Composition of Hardware Components. DAC 1998: 14-19 | |
| 77 | Giuseppe A. Paleologo, Luca Benini, Alessandro Bogliolo, Giovanni De Micheli: Policy Optimization for Dynamic Power Management. DAC 1998: 182-187 | |
| 76 | Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino: Computational Kernels and their Application to Sequential Power Optimization. DAC 1998: 764-769 | |
| 75 | Alessandro Bogliolo, Luca Benini, Giovanni De Micheli: Characterization-Free Behavioral Power Modeling. DATE 1998: 767-773 | |
| 74 | Luca Benini, Giovanni De Micheli, Donatella Sciuto, Enrico Macii, Cristina Silvano: Address Bus Encoding Techniques for System-Level Power Optimization. DATE 1998: 861-866 | |
| 73 | Diego C. Ruspini, Oussama Khatib, Giovanni De Micheli: Hardware-Softw are Run-Time Systems and Robotics: A Case Study Vincent John Mooney III. EUROMICRO 1998: 10162-10167 | |
| 72 | Marco Platzner, Giovanni De Micheli: Acceleration of Satisfiability Algorithms by Reconfigurable Hardware. FPL 1998: 69-78 | |
| 71 | Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino: Timed Supersetting and the Synthesis of Telescopic Units. Great Lakes Symposium on VLSI 1998: 331-337 | |
| 70 | Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino: Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding. Great Lakes Symposium on VLSI 1998: 8-12 | |
| 69 | Shin-ichi Minato, Giovanni De Micheli: Finding all simple disjunctive decompositions using irredundant sum-of-products forms. ICCAD 1998: 111-117 | |
| 68 | Luc Séméria, Giovanni De Micheli: SpC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from C. ICCAD 1998: 340-346 | |
| 67 | James Smith, Giovanni De Micheli: Polynomial methods for component matching and verification. ICCAD 1998: 678-685 | |
| 66 | Luca Benini, Alessandro Bogliolo, Giovanni De Micheli: Dynamic power management of electronic systems. ICCAD 1998: 696-702 | |
| 65 | Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Stefano Quer: Power optimization of core-based systems by address bus encoding. IEEE Trans. VLSI Syst. 6(4): 554-562 (1998) | |
| 64 | Luca Benini, Patrick Vuillod, Giovanni De Micheli: Iterative remapping for logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 948-964 (1998) | |
| 63 | Luca Benini, Enrico Macii, Massimo Poncino, Giovanni De Micheli: Telescopic units: a new paradigm for performance optimization of VLSI designs. IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 220-232 (1998) | |
| 1997 | ||
| 62 | Ellen J. Yoffa, Giovanni De Micheli, Jan M. Rabaey: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997. ACM Press 1997 | |
| 61 | Alessandro Bogliolo, Luca Benini, Giovanni De Micheli: Adaptive least mean square behavioral power modeling. ED&TC 1997: 404-410 | |
| 60 | Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi: Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks. ED&TC 1997: 514-520 | |
| 59 | Luca Benini, Giovanni De Micheli, Enrico Macii, Donatella Sciuto, Cristina Silvano: Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems. Great Lakes Symposium on VLSI 1997: 77-82 | |
| 58 | Patrick Vuillod, Luca Benini, Giovanni De Micheli: Generalized matching from theory to application. ICCAD 1997: 13-20 | |
| 57 | Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi: Fast power estimation for deterministic input streams. ICCAD 1997: 494-501 | |
| 56 | Vincent John Mooney III, Giovanni De Micheli: Real time analysis and priority scheduler generation for hardware-software systems with a synthesized run-time system. ICCAD 1997: 605-612 | |
| 55 | Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Stefano Quer: System-level power optimization of special purpose applications: the beach solution. ISLPED 1997: 24-29 | |
| 54 | Patrick Vuillod, Luca Benini, Giovanni De Micheli: Re-mapping for low power under tight timing constraints. ISLPED 1997: 287-292 | |
| 53 | Luca Benini, Giovanni De Micheli: A survey of Boolean matching techniques for library binding. ACM Trans. Design Autom. Electr. Syst. 2(3): 193-226 (1997) | |
| 52 | Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccò: Gate-level power and current simulation of CMOS integrated circuits. IEEE Trans. VLSI Syst. 5(4): 473-488 (1997) | |
| 51 | Rajesh K. Gupta, Giovanni De Micheli: Specification and analysis of timing constraints for embedded systems. IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 240-256 (1997) | |
| 50 | Rajesh K. Gupta, Giovanni De Micheli: Constrained software synthesis for embedded applications. Journal of Systems Architecture 43(8): 557-586 (1997) | |
| 49 | Luca Benini, Patrick Vuillod, Alessandro Bogliolo, Giovanni De Micheli: Clock Skew Optimization for Peak Current Reduction. VLSI Signal Processing 16(2-3): 117-130 (1997) | |
| 1996 | ||
| 48 | Luca Benini, Alessandro Bogliolo, Giovanni De Micheli: Distributed EDA Tool Integration: The PPP Paradigm. ICCD 1996: 448-453 | |
| 47 | Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccò: Gate-level current waveform simulation of CMOS integrated circuits. ISLPED 1996: 109-112 | |
| 46 | Patrick Vuillod, Luca Benini, Alessandro Bogliolo, Giovanni De Micheli: Clock skew optimization for peak current reduction. ISLPED 1996: 265-270 | |
| 45 | Luca Benini, Patrick Vuillod, Claudionor José Nunes Coelho Jr., Giovanni De Micheli: Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification. ISSS 1996: 57- | |
| 44 | Rajesh K. Gupta, Giovanni De Micheli: A co-synthesis approach to embedded system design automation. Design Autom. for Emb. Sys. 1(1-2): 69-120 (1996) | |
| 43 | Jerry Chih-Yuan Yang, Giovanni De Micheli, Maurizio Damiani: Scheduling and control generation with environmental constraints based on automata representations. IEEE Trans. on CAD of Integrated Circuits and Systems 15(2): 166-183 (1996) | |
| 42 | Luca Benini, Giovanni De Micheli: Automatic synthesis of low-power gated-clock finite-state machines. IEEE Trans. on CAD of Integrated Circuits and Systems 15(6): 630-643 (1996) | |
| 41 | Claudionor José Nunes Coelho Jr., Giovanni De Micheli: Analysis and synthesis of concurrent digital circuits using control-flow expressions. IEEE Trans. on CAD of Integrated Circuits and Systems 15(8): 854-876 (1996) | |
| 1995 | ||
| 40 | Luca Benini, Giovanni De Micheli: Transformation and synthesis of FSMs for low-power gated-clock implementation. ISLPD 1995: 21-26 | |
| 39 | Maurizio Damiani, Jerry Chih-Yuan Yang, Giovanni De Micheli: Optimization of combinational logic circuits based on compatible gates. IEEE Trans. on CAD of Integrated Circuits and Systems 14(11): 1316-1327 (1995) | |
| 1994 | ||
| 38 | Claudionor José Nunes Coelho Jr., Jerry Chih-Yuan Yang, Vincent John Mooney III, Giovanni De Micheli: Redesigning hardware-software systems. CODES 1994: 116-123 | |
| 37 | Rajesh K. Gupta, Giovanni De Micheli: Constrained software generation for hardware-software systems. CODES 1994: 56-63 | |
| 36 | Jerry Chih-Yuan Yang, Giovanni De Micheli, Maurizio Damiani: Scheduling with Environmental Constraints based on Automata Representations. EDAC-ETC-EUROASIC 1994: 495-501 | |
| 35 | Claudionor José Nunes Coelho Jr., Giovanni De Micheli: Dynamic scheduling and synchronization synthesis of concurrent digital systems under system-level constraints. ICCAD 1994: 175-181 | |
| 34 | Polly Siegel, Giovanni De Micheli: Decomposition methods for library binding of speed-independent asynchronous designs. ICCAD 1994: 558-565 | |
| 33 | Jérôme Fron, Jerry Chih-Yuan Yang, Maurizio Damiani, Giovanni De Micheli: A Synthesis Framework Based on Trace and Automata Theory. ISCAS 1994: 291-294 | |
| 32 | Rajesh K. Gupta, Claudionor José Nunes Coelho Jr., Giovanni De Micheli: Program Implementation Schemes for Hardware-Software Systems. IEEE Computer 27(1): 48-55 (1994) | |
| 31 | Luca Benini, Polly Siegel, Giovanni De Micheli: Saving Power by Synthesizing Gated Clocks for Sequential Circuits. IEEE Design & Test of Computers 11(4): 32-41 (1994) | |
| 1993 | ||
| 30 | Polly Siegel, Giovanni De Micheli, David L. Dill: Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs. DAC 1993: 61-67 | |
| 29 | Maurizio Damiani, Jerry Chih-Yuan Yang, Giovanni De Micheli: Optimization of Combinational Logic Circuits Based on Compatible Gates. DAC 1993: 631-636 | |
| 28 | Jerry R. Burch, David L. Dill, Elizabeth Wolf, Giovanni De Micheli: Modeling hierarchical combinational circuits. ICCAD 1993: 612-617 | |
| 27 | Giovanni De Micheli: High-Level Synthesis of Digital Circuits. Advances in Computers 37: 207-283 (1993) | |
| 26 | Rajesh K. Gupta, Giovanni De Micheli: Hardware-Software Cosynthesis for Digital Systems. IEEE Design & Test of Computers 10(3): 29-41 (1993) | |
| 25 | Dave Filo, David C. Ku, Claudionor José Nunes Coelho Jr., Giovanni De Micheli: Interface optimization for concurrent systems under timing constraints. IEEE Trans. VLSI Syst. 1(3): 268-281 (1993) | |
| 24 | Derek C. Wong, Giovanni De Micheli, Michael J. Flynn: Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences. IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 25-46 (1993) | |
| 23 | Maurizio Damiani, Giovanni De Micheli: Don't care set specifications in combinational and synchronous logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(3): 365-388 (1993) | |
| 22 | Frederic Mailhot, Giovanni De Micheli: Algorithms for technology mapping based on binary decision diagrams and on Boolean operations. IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 599-620 (1993) | |
| 1992 | ||
| 21 | Rajesh K. Gupta, Claudionor José Nunes Coelho Jr., Giovanni De Micheli: Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components. DAC 1992: 225-230 | |
| 20 | Maurizio Damiani, Giovanni De Micheli: Recurrence Equations and the Optimization of Synchronous Logic Circuits. DAC 1992: 556-561 | |
| 19 | David C. Ku, Giovanni De Micheli: Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 11(6): 696-718 (1992) | |
| 1991 | ||
| 18 | Silvia Ercolani, Giovanni De Micheli: Technology Mapping for Electrically Programmable Gate Arrays. DAC 1991: 234-239 | |
| 17 | David C. Ku, Dave Filo, Giovanni De Micheli: Control Optimization Based on Resynchronization of Operations. DAC 1991: 366-371 | |
| 16 | Giovanni De Micheli: Synchronous logic synthesis: algorithms for cycle-time minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 10(1): 63-73 (1991) | |
| 1990 | ||
| 15 | David C. Ku, Giovanni De Micheli: Relative Scheduling Under Timing Constraints. DAC 1990: 59-64 | |
| 14 | Frederic Mailhot, Giovanni De Micheli: Technology mapping using boolean matching and don't care sets. EURO-DAC 1990: 212-216 | |
| 13 | Rajesh K. Gupta, Giovanni De Micheli: Partitioning of Functional Models of Synchronous Digital Systems. ICCAD 1990: 216-219 | |
| 12 | Maurizio Damiani, Giovanni De Micheli: Observability Don't Care Sets and Boolean Relations. ICCAD 1990: 502-505 | |
| 11 | Giovanni De Micheli, David C. Ku, Frederic Mailhot, Thomas K. Truong: The Olympus Synthesis System. IEEE Design & Test of Computers 7(5): 37-53 (1990) | |
| 10 | Giovanni De Micheli: Guest Editorial: High-Level Synthesis of Digital Circuits. IEEE Design & Test of Computers 7(5): 6-7 (1990) | |
| 1988 | ||
| 9 | Giovanni De Micheli, David C. Ku: HERCULES - a System for High-Level Synthesis. DAC 1988: 483-488 | |
| 1987 | ||
| 8 | Giovanni De Micheli: Performance-Oriented Synthesis of Large-Scale Domino CMOS Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 6(5): 751-765 (1987) | |
| 1986 | ||
| 7 | Giovanni De Micheli, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Correction to "Optimal State Assignment for Finite State Machines". IEEE Trans. on CAD of Integrated Circuits and Systems 5(1): 239 (1986) | |
| 6 | Giovanni De Micheli: Symbolic Design of Combinational and Sequential Logic Circuits Implemented by Two-Level Logic Macros. IEEE Trans. on CAD of Integrated Circuits and Systems 5(4): 597-616 (1986) | |
| 1985 | ||
| 5 | Giovanni De Micheli, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Optimal State Assignment for Finite State Machines. IEEE Trans. on CAD of Integrated Circuits and Systems 4(3): 269-285 (1985) | |
| 1984 | ||
| 4 | Giovanni De Micheli, Alberto L. Sangiovanni-Vincentelli: Correction to "Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications". IEEE Trans. on CAD of Integrated Circuits and Systems 3(3): 256 (1984) | |
| 1983 | ||
| 3 | Giovanni De Micheli, Alberto L. Sangiovanni-Vincentelli: PLEASURE: a computer program for simple/multiple constrained/unconstrained folding of Programmable Logic Arrays. DAC 1983: 530-537 | |
| 2 | Giovanni De Micheli, Alberto L. Sangiovanni-Vincentelli: Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications. IEEE Trans. on CAD of Integrated Circuits and Systems 2(3): 151-167 (1983) | |
| 1 | Giovanni De Micheli, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli: Symmetric Displacement Algorithms for the Timing Analysis of Large Scale Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 2(3): 167-180 (1983) | |
Colors in the list of coauthors
Last update Sun Jun 3 16:06:10 2012 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page