![]() | ![]() |
Eric G. Mercer
List of publications from the DBLP Bibliography Server - FAQ
| 2012 | ||
|---|---|---|
| 30 | Everett Morse, Nick Vrvilo, Eric Mercer, Jay McCarthy: Modeling Asynchronous Message Passing for C Programs. VMCAI 2012: 332-347 | |
| 2011 | ||
| 29 | Saint Wesonga, Eric G. Mercer, Neha Rungta: Guided test visualization: Making sense of errors in concurrent programs. ASE 2011: 624-627 | |
| 28 | Topher Fischer, Eric Mercer, Neha Rungta: Symbolically modeling concurrent MCAPI executions. PPOPP 2011: 307-308 | |
| 2010 | ||
| 27 | Neha Rungta, Eric Mercer: Slicing and dicing bugs in concurrent programs. ICSE (2) 2010: 195-198 | |
| 2009 | ||
| 26 | Ganesh Gopalakrishnan, Eitan Farchi, Eric Mercer: Proceedings of the 7th Workshop on Parallel and Distributed Systems: Testing, Analysis, and Debugging, PADTAD 2009, Chicago, Illinois, USA, July 19-20, 2009 ACM 2009 | |
| 25 | Subodh Sharma, Ganesh Gopalakrishnan, Eric Mercer, Jim Holt: MCC: A runtime verification tool for MCAPI user applications. FMCAD 2009: 41-44 | |
| 24 | Subodh Sharma, Ganesh Gopalakrishnan, Eric Mercer: Dynamic verification of Multicore Communication applications in MCAPI. HLDVT 2009: 100-105 | |
| 23 | Neha Rungta, Eric G. Mercer: Clash of the Titans: tools and techniques for hunting bugs in concurrent programs. PADTAD 2009 | |
| 22 | Neha Rungta, Eric G. Mercer: Guided model checking for programs with polymorphism. PEPM 2009: 21-30 | |
| 21 | Neha Rungta, Eric G. Mercer, Willem Visser: Efficient Testing of Concurrent Programs with Abstraction-Guided Symbolic Execution. SPIN 2009: 174-191 | |
| 20 | Rahul Kumar, Eric G. Mercer, Annette Bunker: Improving Translation of Live Sequence Charts to Temporal Logic. Electr. Notes Theor. Comput. Sci. 250(1): 137-152 (2009) | |
| 19 | Rahul Kumar, Eric G. Mercer: Verifying Communication Protocols Using Live Sequence Chart Specifications. Electr. Notes Theor. Comput. Sci. 250(2): 33-48 (2009) | |
| 2008 | ||
| 18 | Neha Rungta, Eric G. Mercer: A Meta Heuristic for Effectively Detecting Concurrency Errors. Haifa Verification Conference 2008: 23-37 | |
| 17 | Daniel D. Walker, Eric G. Mercer, Kent E. Seamons: Or Best Offer: A Privacy Policy Negotiation Protocol. POLICY 2008: 173-180 | |
| 16 | Rahul Kumar, Eric G. Mercer: Improving Live Sequence Chart to Automata Transformation for Verification. ECEASST 10: (2008) | |
| 2007 | ||
| 15 | Neha Rungta, Hyrum Carroll, Eric G. Mercer, Randall J. Roper, Mark J. Clement, Quinn Snell: Analyzing Gene Relationships for Down Syndrome with Labeled Transition Graphs. FMCAD 2007: 216-219 | |
| 14 | Neha Rungta, Eric G. Mercer: Hardness for Explicit State Software Model Checking Benchmarks. SEFM 2007: 247-256 | |
| 13 | Joel P. Self, Eric G. Mercer: On-the-Fly Dynamic Dead Variable Analysis. SPIN 2007: 113-130 | |
| 12 | Neha Rungta, Eric G. Mercer: Generating Counter-Examples Through Randomized Guided Search. SPIN 2007: 39-57 | |
| 2006 | ||
| 11 | Neha Rungta, Eric G. Mercer: An Improved Distance Heuristic Function for Directed Software Model Checking. FMCAD 2006: 60-67 | |
| 2005 | ||
| 10 | Neha Rungta, Eric G. Mercer: A context-sensitive structural heuristic for guided search model checking. ASE 2005: 410-413 | |
| 9 | Eric Mercer, Michael Jones: Model Checking Machine Code with the GNU Debugger. SPIN 2005: 251-265 | |
| 8 | Rahul Kumar, Eric G. Mercer: Load Balancing Parallel Explicit State Model Checking. Electr. Notes Theor. Comput. Sci. 128(3): 19-34 (2005) | |
| 2004 | ||
| 7 | Michael Jones, Eric Mercer: Explicit State Model Checking with Hopper. SPIN 2004: 146-150 | |
| 2003 | ||
| 6 | Michael Jones, Eric Mercer, Tonglaga Bao, Rahul Kumar, Peter Lamborn: Benchmarking Explicit State Parallel Model Checkers. Electr. Notes Theor. Comput. Sci. 89(1): 84-98 (2003) | |
| 5 | Hao Zheng, Eric Mercer, Chris J. Myers: Modular verification of timed circuits using automatic abstraction. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1138-1153 (2003) | |
| 2002 | ||
| 4 | Tomoya Kitai, Yusuke Oguro, Tomohiro Yoneda, Eric Mercer, Chris J. Myers: Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method. PRDC 2002: 210-220 | |
| 3 | Eric Mercer, Chris J. Myers, Tomohiro Yoneda: Modular Synthesis of Timed Circuits using Partial Order Reduction. Electr. Notes Theor. Comput. Sci. 65(6): 180-201 (2002) | |
| 2001 | ||
| 2 | Kip C. Killpack, Eric Mercer, Chris J. Myers: A Standard-Cell Self-Timed Multiplier for Energy and Area Critical Synchronous Systems. ARVLSI 2001: 188-201 | |
| 1 | Hao Zheng, Eric Mercer, Chris J. Myers: Automatic Abstraction for Verification of Timed Circuits and Systems. CAV 2001: 182-193 | |
| 1 | Tonglaga Bao | [6] |
| 2 | Annette Bunker | [20] |
| 3 | Hyrum Carroll | [15] |
| 4 | Mark J. Clement | [15] |
| 5 | Eitan Farchi | [26] |
| 6 | Topher Fischer | [28] |
| 7 | Ganesh Gopalakrishnan | [24] [25] [26] |
| 8 | Jim Holt | [25] |
| 9 | Michael Jones | [6] [7] [9] |
| 10 | Kip C. Killpack | [2] |
| 11 | Tomoya Kitai | [4] |
| 12 | Rahul Kumar | [6] [8] [16] [19] [20] |
| 13 | Peter Lamborn | [6] |
| 14 | Jay McCarthy | [30] |
| 15 | Everett Morse | [30] |
| 16 | Chris J. Myers | [1] [2] [3] [4] [5] |
| 17 | Yusuke Oguro | [4] |
| 18 | Randall J. Roper | [15] |
| 19 | Neha Rungta | [10] [11] [12] [14] [15] [18] [21] [22] [23] [27] [28] [29] |
| 20 | Kent E. Seamons | [17] |
| 21 | Joel P. Self | [13] |
| 22 | Subodh Sharma | [24] [25] |
| 23 | Quinn Snell | [15] |
| 24 | Willem Visser | [21] |
| 25 | Nick Vrvilo | [30] |
| 26 | Daniel D. Walker | [17] |
| 27 | Saint Wesonga | [29] |
| 28 | Tomohiro Yoneda | [3] [4] |
| 29 | Hao Zheng (Hank Jayne) | [1] [5] |
Colors in the list of coauthors
Last update Sun Jun 3 16:06:10 2012 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page