James D. Meindl

	2010
40		James D. Meindl, Azad Naeemi, M. Bakir, R. Murali: Nanoelectronics in retrospect, prospect and principle. ISSCC 2010: 31-35
	2008
39		Azad Naeemi, James D. Meindl: Physical models for electron transport in graphene nanoribbons and their junctions. ICCAD 2008: 400-405
38		Kaveh Shakeri, James D. Meindl: Accelerated Modeling of Massively Coupled RLC Interconnects Using the Relative Inductance Extraction Method. IEEE Trans. VLSI Syst. 16(6): 745-754 (2008)
	2007
37		Azad Naeemi, Reza Sarvari, James D. Meindl: Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects. DAC 2007: 568-573
36		Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffrey A. Davis, James D. Meindl: IntSim: A CAD tool for optimization of multilevel interconnect networks. ICCAD 2007: 560-567
35		Azad Naeemi, James D. Meindl: Carbon nanotube interconnects. ISPD 2007: 77-84
	2006
34		Hiren D. Thacker, James D. Meindl: Prospects for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects. ITC 2006: 1-7
	2004
33		James W. Joyner, Payman Zarkesh-Ha, James D. Meindl: Global interconnect design in a three-dimensional system-on-a-chip. IEEE Trans. VLSI Syst. 12(4): 367-372 (2004)
	2003
32		James D. Meindl: Interconnect Opportunities for Gigascale Integration. IEEE Micro 23(3): 28-35 (2003)
31		Lucian Codrescu, S. Nugent, James D. Meindl, D. Scott Wills: Modeling technology impact on cluster microprocessor performance. IEEE Trans. VLSI Syst. 11(5): 909-920 (2003)
	2002
30		Kaveh Shakeri, James D. Meindl: A compact delay model for series-connected MOSFETs. ACM Great Lakes Symposium on VLSI 2002: 37-40
29		Raguraman Venkatesan, Jeffrey A. Davis, James D. Meindl: A physical model for the transient response of capacitively loaded distributed rlc interconnects. DAC 2002: 763-766
28		R. Murali, Lihui Wang, Blanca Austin, James D. Meindl: Low-power circuit advantages of the scaled accumulation FET. ISCAS (5) 2002: 201-204
27		Kaveh Shakeri, James D. Meindl: Temperature Variable Supply Voltage for Power Reduction. ISVLSI 2002: 71-74
26		James D. Meindl, Jeffrey A. Davis, Payman Zarkesh-Ha, Chirag S. Patel, Kevin P. Martin, Paul A. Kohl: Interconnect opportunities for gigascale integration. IBM Journal of Research and Development 46(2-3): 245-264 (2002)
25		A. V. Mule, Elias N. Glytsis, Thomas K. Gaylord, James D. Meindl: Electrical and optical clock distribution networks for gigascale microprocessors. IEEE Trans. VLSI Syst. 10(5): 582-594 (2002)
	2001
24		Martin Saint-Laurent, Madhavan Swaminathan, James D. Meindl: On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs. ICCD 2001: 214-220
23		Azeez J. Bhavnagarwala, Stephen V. Kosonocky, James D. Meindl: Interconnect-centric Array Architectures for Minimum SRAM Access Time. ICCD 2001: 400-405
22		Lucian Codrescu, D. Scott Wills, James D. Meindl: Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications. IEEE Trans. Computers 50(1): 67-82 (2001)
21		Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl: Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI). IEEE Trans. VLSI Syst. 9(6): 899-912 (2001)
20		James W. Joyner, Raguraman Venkatesan, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl: Impact of three-dimensional architectures on interconnects in gigascale integration. IEEE Trans. VLSI Syst. 9(6): 922-928 (2001)
	2000
19		Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoor, James D. Meindl: CMOS system-on-a-chip voltage scaling beyond 50nm. ACM Great Lakes Symposium on VLSI 2000: 7-12
18		Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl: Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion. ISLPED 2000: 167-172
17		Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl: Prediction of interconnect fan-out distribution using Rent's rule. SLIP 2000: 107-112
16		James W. Joyner, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl: Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures. SLIP 2000: 123-127
15		Jeffrey A. Davis, Raguraman Venkatesan, Keith A. Bowman, James D. Meindl: Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session). SLIP 2000: 147-148
14		Azeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman, James D. Meindl: A minimum total power methodology for projecting limits on CMOS GSI. IEEE Trans. VLSI Syst. 8(3): 235-251 (2000)
13		Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl: Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip. IEEE Trans. VLSI Syst. 8(6): 649-659 (2000)
12		Sek M. Chai, Tarek M. Taha, D. Scott Wills, James D. Meindl: Heterogeneous architecture models for interconnect-motivated system design. IEEE Trans. VLSI Syst. 8(6): 660-670 (2000)
11		Qiang Chen, Jeffrey A. Davis, Payman Zarkesh-Ha, James D. Meindl: A compact physical via blockage model. IEEE Trans. VLSI Syst. 8(6): 689-692 (2000)
	1999
10		Lucian Codrescu, Mondira Deb Pant, Tarek M. Taha, John Eble, D. Scott Wills, James D. Meindl: Exploring Microprocessor Architectures for Gigascale Integration. ARVLSI 1999: 242-255
9		James D. Meindl: XXI Century Gigascale Integration (GSI) : The Interconnect Problem. ARVLSI 1999: 88-
	1998
8		Azeez J. Bhavnagarwala, Blanca Austin, James D. Meindl: Minimum supply voltage for bulk Si CMOS GSI. ISLPED 1998: 100-102
	1997
7		James D. Meindl: A history of low power electronics: how it began and where it's headed. ISLPED 1997: 149-151
6		Xinghai Tang, Vivek De, James D. Meindl: Intrinsic MOSFET parameter fluctuations due to random dopant placement. IEEE Trans. VLSI Syst. 5(4): 369-376 (1997)
	1996
5		Azeez J. Bhavnagarwala, Vivek De, Blanca Austin, James D. Meindl: Circuit techniques for low-power CMOS GSI. ISLPED 1996: 193-196
4		Xinghai Tang, Vivek De, James D. Meindl: Effects of random MOSFET parameter fluctuations on total power consumption. ISLPED 1996: 233-236
3		Vivek De, James D. Meindl: A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI). ISLPED 1996: 371-375
	1991
2		James D. Meindl: Design and Test Automation-Gigascale Integration (GSI) in the 21st Century. ICCD 1991: 438
1		James D. Meindl: Gigascale integration (GSI) technology. SC 1991: 534-538

Coauthor Index

1	Blanca Austin	[5] [8] [14] [19] [28]
2	M. Bakir	[40]
3	Azeez J. Bhavnagarwala	[5] [8] [14] [19] [23]
4	Keith A. Bowman	[14] [15] [18] [21]
5	Sek M. Chai	[12]
6	Qiang Chen	[11]
7	Lucian Codrescu	[10] [22] [31]
8	Jeffrey A. Davis	[11] [13] [15] [16] [17] [18] [20] [21] [26] [29] [36]
9	Vivek De (Vivek K. De)	[3] [4] [5] [6]
10	John Eble	[10]
11	Thomas K. Gaylord	[25]
12	Elias N. Glytsis	[25]
13	James W. Joyner	[16] [20] [33]
14	Ashok Kapoor	[19]
15	Paul A. Kohl	[26]
16	Stephen V. Kosonocky	[23]
17	William Loh	[17]
18	Kevin P. Martin	[26]
19	A. V. Mule	[25]
20	R. Murali	[28] [40]
21	Azad Naeemi	[35] [36] [37] [39] [40]
22	S. Nugent	[31]
23	Mondira Deb Pant	[10]
24	Chirag S. Patel	[26]
25	Martin Saint-Laurent	[24]
26	Reza Sarvari	[36] [37]
27	Deepak C. Sekar	[36]
28	Kaveh Shakeri	[27] [30] [38]
29	Madhavan Swaminathan	[24]
30	Tarek M. Taha	[10] [12]
31	Xinghai Tang	[4] [6]
32	Hiren D. Thacker	[34]
33	Raguraman Venkatesan	[15] [18] [20] [21] [29]
34	Lihui Wang	[28]
35	D. Scott Wills	[10] [12] [22] [31]
36	Payman Zarkesh-Ha	[11] [13] [16] [17] [20] [26] [33]

Colors in the list of coauthors

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