Habib Mehrez

	2011
28		Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez: Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA. ARC 2011: 218-229
27		Sophie Belloeil-Dupuis, Roselyne Chotin-Avot, Habib Mehrez: Stratus: Free design of highly parametrized VLSI modules interoperable with commercial tools. ISQED 2011: 502-507
26		Emna Amouri, Zied Marrakchi, Habib Mehrez: Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA. ReCoSoC 2011: 1-4
25		Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi: Exploration of Heterogeneous FPGA Architectures. Int. J. Reconfig. Comp. 2011: (2011)
24		Husain Parvez, Zied Marrakchi, Alp Kilic, Habib Mehrez: Application-Specific FPGA using heterogeneous logic blocks. TRETS 4(3): 24 (2011)
	2010
23		Husain Parvez, Zied Marrakchi, Habib Mehrez: Application Specific FPGA Using Heterogeneous Logic Blocks. ARC 2010: 92-109
22		Husain Parvez, Zied Marrakchi, Habib Mehrez: Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only). FPGA 2010: 290
21		Ludovic Noury, Habib Mehrez: A flexible realtime system for broadband time-frequency analysis in 130 NM CMOS. ICECS 2010: 251-254
	2009
20		Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez: Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA. ICECS 2009: 791-794
19		Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez: Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. ReConFig 2009: 201-206
18		Zied Marrakchi, Hayder Mrabet, Umer Farooq, Habib Mehrez: FPGA Interconnect Topologies Exploration. Int. J. Reconfig. Comp. 2009: (2009)
	2008
17		Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib Mehrez: Efficient tree topology for FPGA interconnect network. ACM Great Lakes Symposium on VLSI 2008: 321-326
16		Sophie Belloeil, Roselyne Chotin-Avot, Habib Mehrez: Arithmetic Data Path Optimization Using Borrow-Save Representation. ISVLSI 2008: 4-9
15		Umer Farooq, Zied Marrakchi, Hayder Mrabet, Habib Mehrez: The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture. ReConFig 2008: 115-120
14		Husain Parvez, Zied Marrakchi, Habib Mehrez: Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-Grained FPGAs. ReConFig 2008: 121-126
13		Ana Abril, Habib Mehrez, Frédéric Pétrot, Jean Gobert, Carolina Miro: Estimation et optimisation de la consommation dans les SoC utilisant la simulation précise au cycle. Technique et Science Informatiques 27(1-2): 203-233 (2008)
	2007
12		Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez: Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances. NOCS 2007: 243-252
	2006
11		Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez: A multilevel hierarchical interconnection structure for FPGA. FPGA 2006: 225
10		Zied Marrakchi, Hayder Mrabet, Habib Mehrez: Configuration tools for a new multilevel hierarchical FPGA. FPGA 2006: 229
9		Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez: Performances improvement of FPGA using novel multilevel hierarchical interconnection structure. ICCAD 2006: 675-679
8		Zied Marrakchi, Hayder Mrabet, Habib Mehrez: A new Multilevel Hierarchical MFPGA and its suitable configuration tools. ISVLSI 2006: 263-268
7		Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez, André Tissot: Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure. ReCoSoC 2006: 117-123
	2005
6		Hayder Mrabet, Zied Marrakchi, Habib Mehrez, André Tissot: Implementation of Scalable Embedded FPGA for SOC. ReCoSoC 2005: 59-62
	2004
5		Roselyne Avot-Chotin, Habib Mehrez: Hardware Implementation of Discrete Stochastic Arithmetic. Numerical Algorithms 37(1-4): 21-33 (2004)
	2000
4		M. Aberbour, Habib Mehrez, François Durbin, Jacques Haussy, P. Lalande, André Tissot: A System-On-A-Chip for Pattern Recognition Architecture and Design Methodology. CAMP 2000: 155-162
	1998
3		M. Aberbour, A. Houelle, Habib Mehrez, N. Vaucher, Alain Guyot: On portable macrocell FPU generators for division and square root operators complying to the full IEEE-754 standard. IEEE Trans. VLSI Syst. 6(1): 114-121 (1998)
	1995
2		A. Houelle, Habib Mehrez, N. Vaucher, Luis A. Montalvo, Alain Guyot: Application of fast layout synthesis environment to dividers evaluation. IEEE Symposium on Computer Arithmetic 1995: 67-74
1		Alain Guyot, Luis A. Montalvo, A. Houelle, Habib Mehrez, N. Vaucher: Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers. VLSI Design 1995: 386-391

Coauthor Index

1	M. Aberbour	[3] [4]
2	Ana Abril	[13]
3	Emna Amouri	[17] [19] [20] [26]
4	Sophie Belloeil-Dupuis (Sophie Belloeil)	[16] [27]
5	Roselyne Chotin-Avot (Roselyne Avot-Chotin)	[5] [16] [27]
6	François Durbin	[4]
7	Umer Farooq	[15] [18] [25] [28]
8	Jean Gobert	[13]
9	Alain Guyot	[1] [2] [3]
10	Jacques Haussy	[4]
11	A. Houelle	[1] [2] [3]
12	Alp Kilic	[24]
13	P. Lalande	[4]
14	Zied Marrakchi	[6] [7] [8] [9] [10] [11] [12] [14] [15] [17] [18] [19] [20] [22] [23] [24] [25] [26] [28]
15	Christian Masson	[12]
16	Carolina Miro	[13]
17	Luis A. Montalvo	[1] [2]
18	Hayder Mrabet	[6] [7] [8] [9] [10] [11] [12] [15] [17] [18] [19] [20]
19	Ludovic Noury	[21]
20	Husain Parvez	[14] [22] [23] [24] [25] [28]
21	Frédéric Pétrot	[13]
22	Pierre Souillot	[7] [9] [11]
23	André Tissot	[4] [6] [7]
24	N. Vaucher	[1] [2] [3]

Colors in the list of coauthors

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