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| 2012 | ||
|---|---|---|
| 64 | Jayakishan Meher, Pramod Kumar Meher, Gananath Dash, Mukesh Kumar Raval: New encoded single-indicator sequences based on physico-chemical parameters for efficient exon identification. IJBRA 8(1/2): 126-140 (2012) | |
| 2011 | ||
| 63 | Chiou-Yng Lee, Pramod Kumar Meher: Speeding up Subquadratic Finite Field Multiplier over GF(2m) Generated by Trinomials Using Toeplitz Matrix-Vector with Inner Product Formula. ICGEC 2011: 232-236 | |
| 62 | Pramod Kumar Meher, Megha Maheshwari: A high-speed FIR adaptive filter architecture using a modified delayed LMS algorithm. ISCAS 2011: 121-124 | |
| 61 | Yu Pan, Pramod Kumar Meher: Efficient coefficient partitioning for decomposed DA-based inner-product computation. ISCAS 2011: 406-409 | |
| 60 | Pramod Kumar Meher, Yu Pan: MCM-based implementation of block FIR filters for high-speed and low-power applications. VLSI-SoC 2011: 118-121 | |
| 59 | Pramod Kumar Meher, Sang Yoon Park: High-throughput pipelined realization of adaptive FIR filter based on distributed arithmetic. VLSI-SoC 2011: 428-433 | |
| 58 | Jagdish Chandra Patra, Pramod Kumar Meher, Goutam Chakraborty: Development of Laguerre Neural-Network-Based Intelligent Sensors for Wireless Sensor Networks. IEEE T. Instrumentation and Measurement 60(3): 725-734 (2011) | |
| 57 | Basant K. Mohanty, Pramod Kumar Meher: Memory-Efficient Architecture for 3-D DWT Using Overlapped Grouping of Frames. IEEE Transactions on Signal Processing 59(11): 5605-5616 (2011) | |
| 56 | Basant K. Mohanty, Pramod Kumar Meher: Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT. IEEE Transactions on Signal Processing 59(5): 2072-2084 (2011) | |
| 55 | Jayakishan Meher, Pramod Kumar Meher, Gananath Dash: Improved Comb Filter based Approach for Effective Prediction of Protein Coding Regions in DNA Sequences. J. Signal and Information Processing 2(2): 88-99 (2011) | |
| 54 | Jayakishan Meher, Mukesh Kumar Raval, Pramod Kumar Meher, Gananath Dash: The Role of Combined OSR and SDF Method for Pre-Processing of Microarray Data that Accounts for Effective Denoising and Quantification. J. Signal and Information Processing 2(3): 190-195 (2011) | |
| 2010 | ||
| 53 | Jagdish Chandra Patra, Jacob Abraham, Pramod Kumar Meher, Goutam Chakraborty: An improved SOM-based visualization technique for DNA microarray data analysis. IJCNN 2010: 1-7 | |
| 52 | Jagdish Chandra Patra, Nyttle V. George, Pramod Kumar Meher: DNA microarray analysis using Equalized Orthogonal Mapping. IJCNN 2010: 1-8 | |
| 51 | Pramod Kumar Meher: Novel input coding technique for high-precision LUT-based multiplication for DSP applications. VLSI-SoC 2010: 201-206 | |
| 50 | Pramod Kumar Meher: An optimized lookup-table for the evaluation of sigmoid function for artificial neural networks. VLSI-SoC 2010: 91-95 | |
| 49 | Chiou-Yng Lee, Pramod Kumar Meher: Efficient bit-parallel multipliers over finite fields GF(2m). Computers & Electrical Engineering 36(5): 955-968 (2010) | |
| 48 | Basant K. Mohanty, Pramod Kumar Meher: Parallel and Pipeline Architectures for High-Throughput Computation of Multilevel 3-D DWT. IEEE Trans. Circuits Syst. Video Techn. 20(9): 1200-1209 (2010) | |
| 47 | Chiou-Yng Lee, Pramod Kumar Meher, Jagdish Chandra Patra: Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over GF(2m) Using Multiple Parity Prediction Schemes. IEEE Trans. VLSI Syst. 18(8): 1234-1238 (2010) | |
| 46 | Pramod Kumar Meher: New Approach to Look-Up-Table Design and Memory-Based Realization of FIR Digital Filter. IEEE Trans. on Circuits and Systems 57-I(3): 592-603 (2010) | |
| 45 | Pramod Kumar Meher: LUT Optimization for Memory-Based Computation. IEEE Trans. on Circuits and Systems 57-II(4): 285-289 (2010) | |
| 44 | Achutavarrier Prasad Vinod, Edmund Ming-Kit Lai, Douglas L. Maskell, Pramod Kumar Meher: An improved common subexpression elimination method for reducing logic operators in FIR filter implementations without increasing logic depth. Integration 43(1): 124-135 (2010) | |
| 43 | Pramod Kumar Meher, Jagdish Chandra Patra, Achutavarrier Prasad Vinod: Efficient Systolic Designs for 1- and 2-Dimensional DFT of General Transform-Lengths for High-Speed Wireless Communication Applications. Signal Processing Systems 60(1): 1-14 (2010) | |
| 2009 | ||
| 42 | Pramod Kumar Meher, Yajun Ha, Chiou-Yng Lee: An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomials. ASP-DAC 2009: 210-215 | |
| 41 | Jagdish Chandra Patra, Nguyen C. Thanh, Pramod Kumar Meher: Computationally efficient FLANN-based intelligent stock price prediction system. IJCNN 2009: 2431-2438 | |
| 40 | Pramod Kumar Meher, Chiou-Yng Lee: Scalable Serial-parallel Multiplier over GF(2m) by Hierarchical Pre-reduction and Input Decomposition. ISCAS 2009: 2910-2913 | |
| 39 | Pramod Kumar Meher: New Approach to LUT Implementation and Accumulation for Memory-based Multiplication. ISCAS 2009: 453-456 | |
| 38 | Pramod Kumar Meher: On Efficient Implementation of Accumulation in Finite Field Over GF(2m) and its Applications. IEEE Trans. VLSI Syst. 17(4): 541-550 (2009) | |
| 37 | Pramod Kumar Meher: Systolic and Non-Systolic Scalable Modular Designs of Finite Field Multipliers for Reed-Solomon Codec. IEEE Trans. VLSI Syst. 17(6): 747-757 (2009) | |
| 36 | Pramod Kumar Meher: Extended Sequential Logic for Synchronous Circuit Optimization and Its Applications. IEEE Trans. on CAD of Integrated Circuits and Systems 28(4): 469-477 (2009) | |
| 35 | Jagdish Chandra Patra, Pramod Kumar Meher, Goutam Chakraborty: Nonlinear channel equalization for wireless communication systems using Legendre neural networks. Signal Processing 89(11): 2251-2262 (2009) | |
| 2008 | ||
| 34 | Chiou-Yng Lee, Pramod Kumar Meher: Efficient Bit-Parallel Multipliers in Composite Fields. APSCC 2008: 686-691 | |
| 33 | Basant K. Mohanty, Pramod Kumar Meher: Concurrent systolic architecture for high-throughput implementation of 3-dimensional discrete wavelet transform. ASAP 2008: 162-166 | |
| 32 | Basant K. Mohanty, Pramod Kumar Meher: Throughput-scalable hybrid-pipeline architecture for multilevel lifting 2-D DWT of JPEG 2000 coder. ASAP 2008: 305-309 | |
| 31 | Pramod Kumar Meher, Jagdish Chandra Patra: Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transform. ASAP 2008: 43-48 | |
| 30 | Pramod Kumar Meher: Efficient systolization of cyclic convolution for systolic implementation of sinusoidal transforms. ASAP 2008: 97-101 | |
| 29 | Sujata Ishwar, Pramod Kumar Meher, M. N. S. Swamy: Discrete tchebichef transform-A fast 4x4 algorithm and its application in image/video compression. ISCAS 2008: 260-263 | |
| 28 | Viet Thang Nguyen, Jagdish Chandra Patra, Pramod Kumar Meher: WMicaD: A New Digital Watermarking Technique Using Independent Component Analysis. EURASIP J. Adv. Sig. Proc. 2008: (2008) | |
| 27 | Pramod Kumar Meher: Parallel and Pipelined Architectures for Cyclic Convolution by Block Circulant Formulation Using Low-Complexity Short-Length Algorithms. IEEE Trans. Circuits Syst. Video Techn. 18(10): 1422-1431 (2008) | |
| 26 | Pramod Kumar Meher: Systolic and Super-Systolic Multipliers for Finite Field GF(2m) Based on Irreducible Trinomials. IEEE Trans. on Circuits and Systems 55-I(4): 1031-1040 (2008) | |
| 25 | Jagdish Chandra Patra, Goutam Chakraborty, Pramod Kumar Meher: Neural-Network-Based Robust Linearization and Compensation Technique for Sensors Under Nonlinear Environmental Influences. IEEE Trans. on Circuits and Systems 55-I(5): 1316-1327 (2008) | |
| 24 | Pramod Kumar Meher, Basant K. Mohanty, Jagdish Chandra Patra: Hardware-Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet Transform. IEEE Trans. on Circuits and Systems 55-II(2): 151-155 (2008) | |
| 23 | Pramod Kumar Meher: New Approach to Scalable Parallel and Pipelined Realization of Repetitive Multiple Accumulations. IEEE Trans. on Circuits and Systems 55-II(9): 902-906 (2008) | |
| 22 | Pramod Kumar Meher, Shrutisagar Chandrasekaran, Abbes Amira: FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic. IEEE Transactions on Signal Processing 56(7-1): 3009-3017 (2008) | |
| 2007 | ||
| 21 | Pramod Kumar Meher: Systolic Formulation for Low-Complexity Serial-Parallel Implementation of Unified Finite Field Multiplication over GF(2m). ASAP 2007: 134-139 | |
| 20 | Jagdish Chandra Patra, Goh P. Lim, Pramod Kumar Meher, Ee-Luang Ang: DNA Microarray Data Analysis: Effective Feature Selection for Accurate Cancer Classification. IJCNN 2007: 260-265 | |
| 2006 | ||
| 19 | Pramod Kumar Meher, A. Prasad Vinod, Jagdish Chandra Patra, M. N. S. Swamy: Reduced-Complexity Concurrent Systolic Implementation of the Discrete Sine Transform. APCCAS 2006: 1535-1538 | |
| 18 | A. Prasad Vinod, Chip-Hong Chang, Pramod Kumar Meher, Ankita Singla: Low Power FIR Filter Realization using Minimal Difference Coefficients: Part I - Complexity Analysis. APCCAS 2006: 1547-1550 | |
| 17 | A. Prasad Vinod, Chip-Hong Chang, Pramod Kumar Meher, Ankita Singla: Low Power FIR Filter Realization Using Minimal Difference Coefficients: Part II - Algorithm. APCCAS 2006: 1551-1554 | |
| 16 | Pramod Kumar Meher, Jagdish Chandra Patra, A. Prasad Vinod: A 2-D Systolic Array for High-Throughput Computation of 2-D Discrete Fourier Transform. APCCAS 2006: 1927-1930 | |
| 15 | Jagdish Chandra Patra, W. Soh, Ee-Luang Ang, Pramod Kumar Meher: An Improved SVD-Based Watermarking Technique for Image and Document Authentication. APCCAS 2006: 1984-1987 | |
| 14 | Basant K. Mohanty, Pramod Kumar Meher: VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT. APCCAS 2006: 458-461 | |
| 13 | Basant K. Mohanty, Pramod Kumar Meher: Merged-Cascaded Systolic Array for VLSI Implementation of Discrete Wavelet Transform. APCCAS 2006: 462-465 | |
| 12 | Jagdish Chandra Patra, Han Yang Lee, Pramod Kumar Meher, Ee-Luang Ang: Field Programmable Gate Array Implementation of a Neural Network-based Intelligent Sensor System. ICARCV 2006: 1-5 | |
| 11 | Jagdish Chandra Patra, Weineng Lim, Pramod Kumar Meher, Ee-Luang Ang: Financial Prediction of Major Indices using Computational Efficient Artificial Neural Networks. IJCNN 2006: 2114-2120 | |
| 10 | Jagdish Chandra Patra, Ee-Luang Ang, Pramod Kumar Meher, Qin Zhen: A New SOM-based Visualization Technique for DNA Microarray Data. IJCNN 2006: 4429-4434 | |
| 9 | Pramod Kumar Meher, Jagdish Chandra Patra: A new approach to secure distributed storage, sharing and dissemination of digital image. ISCAS 2006 | |
| 8 | Jagdish Chandra Patra, Ee-Luang Ang, Pramod Kumar Meher: A novel neural network-based linearization and auto-compensation technique for sensors. ISCAS 2006 | |
| 7 | Pramod Kumar Meher, Jagdish Chandra Patra, M. R. Meher: Low-complexity technique for secure storage and sharing of biomedical images. ISCAS 2006 | |
| 6 | Pramod Kumar Meher: Systolic Designs for DCT Using a Low-Complexity Concurrent Convolutional Formulation. IEEE Trans. Circuits Syst. Video Techn. 16(9): 1041-1050 (2006) | |
| 2005 | ||
| 5 | Pramod Kumar Meher: Area-Time Efficient Systolic Architecture for the DCT. Asia-Pacific Computer Systems Architecture Conference 2005: 787-794 | |
| 2003 | ||
| 4 | Pramod Kumar Meher, Thambipillai Srikanthan, M. Mahesh Kumar, S. Arunkumar: Low-Power Transform-Domain Coding by Separable Two-Dimensional Hartley-Like Transform. Embedded Systems and Applications 2003: 228-236 | |
| 2002 | ||
| 3 | Prafulla Kumar Behera, Pramod Kumar Meher: Effective communication in ad hoc network of mobile users group. APCCAS (2) 2002: 461-465 | |
| 2 | A. K. Rath, Pramod Kumar Meher: Reconfigurable execution core for high performance DSP applications. APCCAS (2) 2002: 509-514 | |
| 1 | Prafulla Kumar Behera, Pramod Kumar Meher: Prospects of Group-Based Communication in Mobile Ad hoc Networks. IWDC 2002: 174-183 | |
Colors in the list of coauthors
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