Mahesh Mehendale

	2012
34		Mahesh Mehendale, Subrangshu Das, Mohit Sharma, Mihir Mody, Ratna Reddy, Joseph Meehan, Hideo Tamama, Brian Carlson, Mike Polley: A true multistandard, programmable, low-power, full HD video-codec engine for smartphone SoC. ISSCC 2012: 226-228
	2011
33		Nagendra Gulur, R. Manikantan, R. Govindarajan, Mahesh Mehendale: Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs. PACT 2011: 189-190
32		Ajit Gupte, Bharadwaj Amrutur, Mahesh Mehendale, Ajit V. Rao, Madhukar Budagavi: Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding. IEEE Trans. Circuits Syst. Video Techn. 21(2): 225-230 (2011)
	2006
31		Mahesh Mehendale: SoC - The Road Ahead. VLSI Design 2006: 40
30		Subash G. Chandar, Mahesh Mehendale, R. Govindarajan: Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding. VLSI Signal Processing 44(3): 245-267 (2006)
	2004
29		Mahesh Mehendale: Challenges in the Design of Embedded Real-time DSP SoCs. VLSI Design 2004: 507-511
	2003
28		Chi-Foon Chan, Deirdre Hanford, Jian Yue Pan, Narendra V. Shenoy, Mahesh Mehendale, A. Vasudevan, Shaojun Wei: Emerging markets: design goes global. DAC 2003: 195
27		Amitabh Menon, S. K. Nandy, Mahesh Mehendale: Multivoltage scheduling with voltage-partitioned variable storage. ISLPED 2003: 298-301
	2001
26		Subash G. Chandar, Mahesh Mehendale, R. Govindarajan: Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-Configurable Encoding. ICCAD 2001: 631-634
25		Mahesh Mehendale, Santhosh Kumar Amanna: Functional Verification of Programmable DSP Cores. VLSI Design 2001: 16-17
24		Ajit Gupte, Mahesh Mehendale, Ramesh Ramamritham, Deepa Nair: Performance Considerations in Embedded DSP based System-On-a-Chip Designs. VLSI Design 2001: 36-41
23		Vikas Agrawal, Anand Pande, Mahesh Mehendale: High Level Synthesis Of Multi-Precision Data Flow Graphs. VLSI Design 2001: 411-416
	2000
22		Mahesh Mehendale, Sunil D. Sherlekar: Power Reduction Techniques for Portable DSP Applications. VLSI Design 2000: 3
21		M. N. Mahesh, Mahesh Mehendale: Low Power Realization of Residue Number System Based FIR Filters. VLSI Design 2000: 30-33
	1999
20		M. N. Mahesh, Mahesh Mehendale: Improving performance of high precision signal processing algorithms on programmable DSPs. ISCAS (3) 1999: 488-491
19		M. N. Mahesh, Satrajit Gupta, Mahesh Mehendale: Improving Area Efficiency of Residue Number System based Implementation of DSP Algorithms. VLSI Design 1999: 340-345
18		Mahesh Mehendale, Sunil D. Sherlekar: Low Power Code Generation of Multiplication-free Linear Transforms. VLSI Design 1999: 42-47
	1998
17		Mahesh Mehendale, Amit Sinha, Sunil D. Sherlekar: Low Power Realization of FIR Filters Implemented using Distributed Arithmetic. ASP-DAC 1998: 151-156
16		Amit Sinha, Mahesh Mehendale: mproving Area Efficiency of FIR Filters Implemented Using Distributed Arithmetic. VLSI Design 1998: 104-109
15		Mahesh Mehendale, Somdipta Basu Roy, Sunil D. Sherlekar, G. Venkatesh: Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters. VLSI Design 1998: 110-115
14		Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh: Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters. VLSI Design 1998: 12-17
13		Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh: Extensions to Programmable DSP architectures for Reduced Power Dissipation. VLSI Design 1998: 37-
12		Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh: Low-power realization of FIR filters on programmable DSPs. IEEE Trans. VLSI Syst. 6(4): 546-553 (1998)
	1997
11		Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh: Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters. VLSI Design 1997: 124-129
	1996
10		Mahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar: Optimized Code Generation of Multiplication-free Linear Transforms. DAC 1996: 41-46
9		Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh: Low power realization of FIR filters using multirate architectures. VLSI Design 1996: 370-375
	1995
8		Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh: Techniques for low power realization for FIR filters. ASP-DAC 1995
7		Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh: Synthesis of multiplier-less FIR filters with minimum number of additions. ICCAD 1995: 668-671
6		Mahesh Mehendale, M. K. Ram Prasad: AATMA: an algorithm for technology mapping for antifuse-based FPGAs. VLSI Design 1995: 69-74
	1994
5		Mahesh Mehendale: Impact of Logic Module Routing Flexibility on the Routability of Antifuse-Based Channelled FPGA Architectures. VLSI Design 1994: 233-236
4		Mahesh Mehendale, Biswadip Mitra: An Integrated Approach to State Assignment and Sequential Element Selection for FSM Synthesis. VLSI Design 1994: 369-372
	1993
3		Mahesh Mehendale: MIM: Logic Module Independent Technology Mapping for Design and Evaluation of Antifuse-based FPGAs. DAC 1993: 219-223
2		Mahesh Mehendale, Kaushik Roy: Estimating Area Efficiency of Antifuse Based Channelled FPGA Architectures. VLSI Design 1993: 100-103
	1991
1		Mahesh Mehendale, P. Murugavel, M. Poornima: SLIM: A System for ASIC Library Management. ICCAD 1991: 144-147

Coauthor Index

1	Vikas Agrawal	[23]
2	Santhosh Kumar Amanna	[25]
3	Bharadwaj S. Amrutur (Bharadwaj Amrutur)	[32]
4	Madhukar Budagavi	[32]
5	Brian Carlson	[34]
6	Chi-Foon Chan	[28]
7	Subash G. Chandar	[26] [30]
8	Subrangshu Das	[34]
9	R. Govindarajan (Ramaswamy Govindarajan)	[26] [30] [33]
10	Nagendra Gulur	[33]
11	Satrajit Gupta	[19]
12	Ajit Gupte	[24] [32]
13	Deirdre Hanford	[28]
14	M. N. Mahesh	[19] [20] [21]
15	R. Manikantan	[33]
16	Joseph Meehan	[34]
17	Amitabh Menon	[27]
18	Biswadip Mitra	[4]
19	Mihir Mody	[34]
20	P. Murugavel	[1]
21	Deepa Nair	[24]
22	S. K. Nandy (Soumitra Kumar Nandy)	[27]
23	Jian Yue Pan	[28]
24	Anand Pande	[23]
25	Mike Polley	[34]
26	M. Poornima	[1]
27	M. K. Ram Prasad	[6]
28	Ramesh Ramamritham	[24]
29	Ajit V. Rao	[32]
30	Ratna Reddy	[34]
31	Kaushik Roy	[2]
32	Somdipta Basu Roy	[15]
33	Mohit Sharma	[34]
34	Narendra V. Shenoy	[28]
35	Sunil D. Sherlekar	[7] [8] [9] [10] [11] [12] [13] [14] [15] [17] [18] [22]
36	Amit Sinha	[16] [17]
37	Hideo Tamama	[34]
38	A. Vasudevan	[28]
39	G. Venkatesh	[7] [8] [9] [10] [11] [12] [13] [14] [15]
40	Shaojun Wei	[28]

Colors in the list of coauthors

Last update Sun Jun 3 16:06:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page