 | 2011 |
| 23 |  | Majdi Elhaji,
Brahim Attia,
Abdelkrim Zitouni,
Rached Tourki,
Samy Meftali,
Jean-Luc Dekeyser:
FeRoNoC: Flexible and extensible Router implementation for diagonal mesh topology.
DASIP 2011: 269-276 |
| 22 |  | Sana Cherif,
Chiraz Trabelsi,
Samy Meftali,
Jean-Luc Dekeyser:
High level design of adaptive distributed controller for partial dynamic reconfiguration in FPGA.
DASIP 2011: 308-315 |
| 21 |  | Chiraz Trabelsi,
Rabie Ben Atitallah,
Samy Meftali,
Jean-Luc Dekeyser,
Abderrazek Jemai:
A Model-Driven Approach for Hybrid Power Estimation in Embedded Systems Design.
EURASIP J. Emb. Sys. 2011: (2011) |
| 2010 |
| 20 |  | Imran Rafiq Quadri,
Samy Meftali,
Jean-Luc Dekeyser:
Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation.
DASIP 2010: 68-75 |
| 19 |  | Sana Cherif,
Imran Rafiq Quadri,
Samy Meftali,
Jean-Luc Dekeyser:
Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis.
DSD 2010: 706-713 |
| 18 |  | Majdi Elhaji,
Abdelkrim Zitouni,
Samy Meftali,
Jean-Luc Dekeyser,
Rached Tourki:
A Low power and highly parallel implementation of the H.264 8 × 8 transform and quantization.
ISSPIT 2010: 528-531 |
| 17 |  | Imran Rafiq Quadri,
Huafeng Yu,
Abdoulaye Gamatié,
Éric Rutten,
Samy Meftali,
Jean-Luc Dekeyser:
Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation.
IJES 4(3/4): 204-224 (2010) |
| 2008 |
| 16 |  | Imran Rafiq Quadri,
Samy Meftali,
Jean-Luc Dekeyser:
MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs.
ESTImedia 2008: 47-52 |
| 15 |  | Imran Rafiq Quadri,
Pierre Boulet,
Samy Meftali,
Jean-Luc Dekeyser:
Using an MDE Approach for Modeling of Interconnection Networks.
ISPAN 2008: 289-294 |
| 2007 |
| 14 |  | Philippe Marquet,
Simon Duquennoy,
Sébastien Le Beux,
Samy Meftali,
Jean-Luc Dekeyser:
Massively parallel processing on a chip.
Conf. Computing Frontiers 2007: 277-286 |
| 13 |  | Rabie Ben Atitallah,
Smaïl Niar,
Samy Meftali,
Jean-Luc Dekeyser:
An MPSoC Performance Estimation Framework Using Transaction Level Modeling.
RTCSA 2007: 525-533 |
| 2006 |
| 12 |  | Rabie Ben Atitallah,
Smaïl Niar,
Alain Greiner,
Samy Meftali,
Jean-Luc Dekeyser:
Estimating Energy Consumption for an MPSoC Architectural Exploration.
ARCS 2006: 298-310 |
| 2005 |
| 11 |  | Samy Meftali,
Anouar Dziri,
Luc Charest,
Philippe Marquet,
J. Deskeyser:
SOAP Based Distributed Simulation Environment for SoC Design.
FDL 2005: 283-291 |
| 10 |  | J. Vennin,
S. Penain,
Luc Charest,
Samy Meftali,
Jean-Luc Dekeyser:
Embed Scripting inside SystemC.
FDL 2005: 373-385 |
| 9 |  | Samy Meftali,
Jean-Luc Dekeyser,
Isaac D. Scherson:
Scalable Multistage Network for Multiprocessor System-on-Chip Design.
ISPAN 2005: 352-357 |
| 2004 |
| 8 |  | E. Turbatu,
Samy Meftali,
Smaïl Niar,
Jean-Luc Dekeyser:
An automatic communication synthesis for high level SOC desing using transaction level modelling (poster).
FDL 2004: 378-380 |
| 7 |  | M. Samyn,
Samy Meftali,
Jean-Luc Dekeyser:
MDA Based, SystemC Code Generation, Applied to Intensive Signal Processing Applications.
FDL 2004: 452-463 |
| 6 |  | Samy Meftali,
Jean-Luc Dekeyser:
An Optimal Charge Balancing Model for Fast Distributed SystemC Simulation in IP/SoC Design.
IWSOC 2004: 55-58 |
| 5 |  | Samy Meftali,
Jean-Luc Dekeyser:
SoCP2P: A Peer-to-Peer IPS Based SoC Design and Simulation Tool.
Virtual Enterprises and Collaborative Networks 2004: 387-394 |
| 2002 |
| 4 |  | Ferid Gharsalli,
Samy Meftali,
Frédéric Rousseau,
Ahmed Amine Jerraya:
Automatic generation of embedded memory wrapper for multiprocessor SoC.
DAC 2002: 596-601 |
| 3 |  | Ahmed Amine Jerraya,
Damien Lyonnard,
Samy Meftali,
Frédéric Rousseau,
Ferid Gharsalli:
Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design.
ISSS 2002: 26-31 |
| 2001 |
| 2 |  | Samy Meftali,
Ferid Gharsalli,
Frédéric Rousseau,
Ahmed Amine Jerraya:
An optimal memory allocation for application-specific multiprocessor system-on-chip.
ISSS 2001: 19-24 |
| 1 |  | Samy Meftali,
Ferid Gharsalli,
Frédéric Rousseau,
Ahmed Amine Jerraya:
Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory.
VLSI-SOC 2001: 193-204 |