Edward J. McCluskey

	2010
181		Ahmad A. Al-Yamani, Edward J. McCluskey: Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns. J. Electronic Testing 26(5): 513-521 (2010)
	2008
180		Jaekwang Lee, Edward J. McCluskey: Failing Frequency Signature Analysis. ITC 2008: 1-8
179		Intaik Park, Edward J. McCluskey: Launch-on-Shift-Capture Transition Tests. ITC 2008: 1-9
178		François-Fabien Ferhani, Nirmal R. Saxena, Edward J. McCluskey, Phil Nigh: How Many Test Patterns are Useless? VTS 2008: 23-28
177		Jaekwang Lee, Intaik Park, Edward J. McCluskey: Error Sequence Analysis. VTS 2008: 255-260
176		Intaik Park, Donghwi Lee, Erik Chmelar, Edward J. McCluskey: Inconsistent Fail due to Limited Tester Timing Accuracy. VTS 2008: 47-52
	2007
175		Kyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey: California scan architecture for high quality and low power testing. ITC 2007: 1-10
174		Kyoung Youn Cho, Edward J. McCluskey: Test Set Reordering Using the Gate Exhaustive Test Metric. VTS 2007: 199-204
	2006
173		François-Fabien Ferhani, Edward J. McCluskey: Classifying Bad Chips and Ordering Test Sets. ITC 2006: 1-10
172		Erik Chmelar, Edward J. McCluskey: Session Abstract. VTS 2006: 156-157
	2005
171		Ahmad A. Al-Yamani, Edward J. McCluskey: BIST-Guided ATPG. ISQED 2005: 244-249
170		Kyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey: Gate exhaustive testing. ITC 2005: 7
169		Intaik Park, Ahmad A. Al-Yamani, Edward J. McCluskey: Effective TARO Pattern Generation. VTS 2005: 161-166
168		Ahmad A. Al-Yamani, Edward J. McCluskey: Test chip experimental results on high-level structural test. ACM Trans. Design Autom. Electr. Syst. 10(4): 690-701 (2005)
167		Chien-Mo James Li, Edward J. McCluskey: Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1748-1759 (2005)
166		Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey: Optimized reseeding by seed ordering and encoding. IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 264-270 (2005)
	2004
165		Kenneth A. Brand, Erik H. Volkerink, Edward J. McCluskey, Subhasish Mitra: Speed Clustering of Integrated Circuits. ITC 2004: 1128-1137
164		Mehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure: A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs. VTS 2004: 154-170
163		Edward J. McCluskey, Ahmad A. Al-Yamani, Chien-Mo James Li, Chao-Wen Tseng, Erik H. Volkerink, François-Fabien Ferhani, Edward Li, Subhasish Mitra: ELF-Murphy Data on Defects and Test Sets. VTS 2004: 16-22
162		Subhasish Mitra, Erik H. Volkerink, Edward J. McCluskey, Stefan Eichenberger: Delay Defect Screening using Process Monitor Structures. VTS 2004: 43-52
161		Subhasish Mitra, Wei-Je Huang, Nirmal R. Saxena, Shu-Yi Yu, Edward J. McCluskey: Reconfigurable Architecture for Autonomous Self-Repair. IEEE Design & Test of Computers 21(3): 228-240 (2004)
160		Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey: Efficient Design Diversity Estimation for Combinational Circuits. IEEE Trans. Computers 53(11): 1483-1492 (2004)
	2003
159		Ahmad A. Al-Yamani, Edward J. McCluskey: Seed encoding with LFSRs and cellular automata. DAC 2003: 560-565
158		Ahmad A. Al-Yamani, Edward J. McCluskey: Built-In Reseeding for Serial Bist. VTS 2003: 63-68
157		Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey: Bist Reseeding with very few Seeds. VTS 2003: 69-76
	2002
156		Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey: Testing Digital Circuits with Constraints. DFT 2002: 195-206
155		Subhasish Mitra, Edward J. McCluskey: Dependable Reconfigurable Computing Design Diversity and Self Repair. Evolvable Hardware 2002: 5
154		Mehdi Baradaran Tahoori, Subhasish Mitra, Shahin Toutounchi, Edward J. McCluskey: Fault Grading FPGA Interconnect Test Configurations. ITC 2002: 608-617
153		Chien-Mo James Li, Edward J. McCluskey: Diagnosis of Sequence-Dependent Chips. VTS 2002: 187-192
152		Subhasish Mitra, Edward J. McCluskey, Samy Makar: Design for Testability and Testing of IEEE 1149.1 Tap Controller. VTS 2002: 247-252
151		Edward J. McCluskey, Subhasish Mitra, Bob Madge, Peter C. Maxwell, Phil Nigh, Mike Rodgers: Debating the Future of Burn-In. VTS 2002: 311-314
150		Chao-Wen Tseng, James Li, Edward J. McCluskey: Experimental Results for Slow-Speed Testing. VTS 2002: 37-42
149		Nahmsuk Oh, Subhasish Mitra, Edward J. McCluskey: ED4I: Error Detection by Diverse Data and Duplicated Instructions. IEEE Trans. Computers 51(2): 180-199 (2002)
148		Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey: A Design Diversity Metric and Analysis of Redundant Systems. IEEE Trans. Computers 51(5): 498-510 (2002)
	2001
147		Shu-Yi Yu, Edward J. McCluskey: Permanent Fault Repair for FPGAs with Limited Redundant Area. DFT 2001: 125-133
146		Nahmsuk Oh, Edward J. McCluskey: Procedure Call Duplication: Minimization of Energy Consumption with Constrained Error Detection Latency. DFT 2001: 182-
145		Wei-Je Huang, Subhasish Mitra, Edward J. McCluskey: Fast Run-Time Fault Location in Dependable FPGA-Based Applications. DFT 2001: 206-214
144		Ahmad A. Al-Yamani, Nahmsuk Oh, Edward J. McCluskey: Performance Evaluation of Checksum-Based ABFT. DFT 2001: 461-
143		Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey: Techniques for Estimation of Design Diversity for Combinational Logic Circuits. DSN 2001: 25-36
142		Wei-Je Huang, Edward J. McCluskey: A memory coherence technique for online transient error recovery of FPGA configurations. FPGA 2001: 183-192
141		Subhasish Mitra, Edward J. McCluskey: Diversity Techniques for Concurrent Error Detection. ISQED 2001: 249-250
140		Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey: Testing for resistive opens and stuck opens. ITC 2001: 1049-1058
139		Shu-Yi Yu, Edward J. McCluskey: On-line testing and recovery in TMR systems for real-time applications. ITC 2001: 240-249
138		Chao-Wen Tseng, Edward J. McCluskey: Multiple-output propagation transition fault test. ITC 2001: 358-366
137		Subhasish Mitra, Edward J. McCluskey: Design Diversity for Concurrent Error Detection in Sequential Logic Circuts. VTS 2001: 178-183
136		Subhasish Mitra, Edward J. McCluskey: Design of Redundant Systems Protected Against Common-Mode Failures. VTS 2001: 190-197
135		Chien-Mo James Li, Edward J. McCluskey: Diagnosis of Tunneling Opens. VTS 2001: 22-27
134		Chao-Wen Tseng, Ray Chen, Edward J. McCluskey, Phil Nigh: MINVDD Testing for Weak CMOS ICs. VTS 2001: 339-345
133		Chao-Wen Tseng, Subhasish Mitra, Edward J. McCluskey, Scott Davidson: An Evaluation of Pseudo Random Testing for Detecting Real Defects. VTS 2001: 404-410
132		Nur A. Touba, Edward J. McCluskey: Bit-fixing in pseudorandom sequences for scan BIST. IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 545-555 (2001)
	2000
131		Shu-Yi Yu, Nirmal R. Saxena, Edward J. McCluskey: An ACS Robotic Control Algorithm with Fault Tolerant Capabilities. FCCM 2000: 175-184
130		Wei-Je Huang, Nirmal R. Saxena, Edward J. McCluskey: A Reliable LZ Data Compressor on Reconfigurable Coprocessors. FCCM 2000: 249-258
129		Subhasish Mitra, Edward J. McCluskey: Combinational logic synthesis for diversity in duplex systems. ITC 2000: 179-188
128		Edward J. McCluskey, Chao-Wen Tseng: Stuck-fault tests vs. actual defects. ITC 2000: 336-343
127		Chien-Mo James Li, Edward J. McCluskey: Testing for tunneling opens. ITC 2000: 85-94
126		Subhasish Mitra, Edward J. McCluskey: Which concurrent error detection scheme to choose ? ITC 2000: 985-994
125		Wei-Je Huang, Edward J. McCluskey: Transient errors and rollback recovery in LZ compression. PRDC 2000: 128-138
124		Chao-Wen Tseng, Edward J. McCluskey, Xiaoping Shao, David M. Wu: Cold Delay Defect Screening. VTS 2000: 183-188
123		Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey: Fault Escapes in Duplex Systems. VTS 2000: 453-458
122		Subhasish Mitra, Edward J. McCluskey: Word Voter: A New Voter Design for Triple Modular Redundant Systems. VTS 2000: 465-470
121		Nirmal R. Saxena, Santiago Fernández-Gomez, Wei-Je Huang, Subhasish Mitra, Shu-Yi Yu, Edward J. McCluskey: Dependable Computing and Online Testing in Adaptive and Configurable Systems. IEEE Design & Test of Computers 17(1): 29-41 (2000)
120		Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey: Efficient Multiplexer Synthesis Techniques. IEEE Design & Test of Computers 17(4): 90-97 (2000)
	1999
119		Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey: A design diversity metric and reliability analysis for redundant systems. ITC 1999: 662-671
118		Chaohuang Zeng, Nirmal R. Saxena, Edward J. McCluskey: Finite state machine synthesis with concurrent error detection. ITC 1999: 672-679
117		Philip P. Shirvani, Edward J. McCluskey: PADded Cache: A New Fault-Tolerance Technique for Cache Memories. VTS 1999: 440-445
116		Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey: An output encoding problem and a solution technique. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 761-768 (1999)
115		Nur A. Touba, Edward J. McCluskey: RP-SYN: synthesis of random pattern testable circuits with test point insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 18(8): 1202-1213 (1999)
	1998
114		Jonathan T.-Y. Chang, Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey: Analysis of pattern-dependent and timing-dependent failures in an experimental test chip. ITC 1998: 184-193
113		Jonathan T.-Y. Chang, Edward J. McCluskey: Detecting resistive shorts for CMOS domino circuits. ITC 1998: 890-899
112		Jonathan T.-Y. Chang, Chao-Wen Tseng, Yi-Chin Chu, Sanjay Wattal, Mike Purtell, Edward J. McCluskey: Experimental Results for IDDQ and VLV Testing. VTS 1998: 118-125
	1997
111		Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey: An output encoding problem and a solution technique. ICCAD 1997: 304-307
110		Nur A. Touba, Edward J. McCluskey: Pseudo-Random Pattern Testing of Bridging Faults. ICCD 1997: 54-60
109		Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey: Scan Synthesis for One-Hot Signals. ITC 1997: 714-722
108		Samy Makar, Edward J. McCluskey: ATPG for scan chain latches and flip-flops. VTS 1997: 364-369
107		Robert B. Norwood, Edward J. McCluskey: High-Level Synthesis for Orthogonal Sca. VTS 1997: 370-375
106		Jonathan T.-Y. Chang, Edward J. McCluskey: SHOrt voltage elevation (SHOVE) test for weak CMOS ICs. VTS 1997: 446-
105		Nirmal R. Saxena, Edward J. McCluskey: Parallel Signatur Analysis Design with Bounds on Aliasing. IEEE Trans. Computers 46(4): 425-438 (1997)
104		Nur A. Touba, Edward J. McCluskey: Logic synthesis of multilevel circuits with concurrent error detection. IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 783-789 (1997)
	1996
103		Nur A. Touba, Edward J. McCluskey: Altering a Pseudo-Random Bit Sequence for Scan-Based BIST. ITC 1996: 167-175
102		Jonathan T.-Y. Chang, Edward J. McCluskey: Detecting Delay Flaws by Very-Low-Voltage Testing. ITC 1996: 367-376
101		Robert B. Norwood, Edward J. McCluskey: Orthogonal Scan: Low-Overhead Scan for Data Paths. ITC 1996: 659-668
100		Piero Franco, Siyad C. Ma, Jonathan Chang, Yi-Chin Chu, Sanjay Wattal, Edward J. McCluskey, Robert L. Stokes, William D. Farwell: Analysis and Detection of Timing Failures in an Experimental Test Chip. ITC 1996: 691-700
99		Nur A. Touba, Edward J. McCluskey: Test point insertion based on path tracing. VTS 1996: 2-8
98		Jonathan T.-Y. Chang, Edward J. McCluskey: Quantitative analysis of very-low-voltage testing. VTS 1996: 332-337
97		Nur A. Touba, Edward J. McCluskey: Applying two-pattern tests using scan-mapping. VTS 1996: 393-399
96		Robert B. Norwood, Edward J. McCluskey: Synthesis-for-scan and scan chain ordering. VTS 1996: 87-92
95		Nirmal R. Saxena, Edward J. McCluskey: Counting Two-State Transition-Tour Sequences. IEEE Trans. Computers 45(11): 1337-1342 (1996)
	1995
94		Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey: A simple technique for locating gate-level faults in combinational circuits. Asian Test Symposium 1995: 65-70
93		Samy Makar, Edward J. McCluskey: Functional Tests for Scan Chain Latches. ITC 1995: 606-615
92		Piero Franco, William D. Farwell, Robert L. Stokes, Edward J. McCluskey: An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design. ITC 1995: 653-662
91		Siyad C. Ma, Piero Franco, Edward J. McCluskey: An Experimental Chip to Evaluate Test Techniques: Experiment Results. ITC 1995: 663-672
90		Nur A. Touba, Edward J. McCluskey: Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST. ITC 1995: 674-682
89		Shridhar K. Mukund, Edward J. McCluskey, T. R. N. Rao: An apparatus for pseudo-deterministic testing. VTS 1995: 125-131
88		Samy Makar, Edward J. McCluskey: Checking experiments to test latches. VTS 1995: 196-201
87		Nur A. Touba, Edward J. McCluskey: Transformed pseudo-random patterns for BIST. VTS 1995: 410-416
86		Daniel Boley, Gene H. Golub, Samy Makar, Nirmal R. Saxena, Edward J. McCluskey: Floating Point Fault Tolerance with Backward Error Assertions. IEEE Trans. Computers 44(2): 302-311 (1995)
85		Siyad C. Ma, Edward J. McCluskey: Open faults in BiCMOS gates. IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 567-575 (1995)
84		Kiyoshi Furuya, Seiji Seki, Edward J. McCluskey: Design of Autonomous TPG Circuits for Use in Two-Pattern Testing. IEICE Transactions 78-D(7): 882-888 (1995)
	1994
83		Nur A. Touba, Edward J. McCluskey: Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection. ICCAD 1994: 651-654
82		Nur A. Touba, Edward J. McCluskey: Automated Logic Synthesis of Random-Pattern-Testable Circuits. ITC 1994: 174-183
81		Nirmal R. Saxena, Edward J. McCluskey: Linear Complexity Assertions for Sorting. IEEE Trans. Software Eng. 20(6): 424-431 (1994)
	1993
80		Hong Hao, Edward J. McCluskey: Very-Low-Voltage Testing for Weak CMOS Logic ICs. ITC 1993: 275-284
79		Edward J. McCluskey: Quality and Single-Stuck Faults. ITC 1993: 597
78		LaNae J. Avra, Edward J. McCluskey: Synthesizing for Scan Dependence in Built-In Self-Testable Desings. ITC 1993: 734-743
77		Hong Hao, Edward J. McCluskey: Analysis of Gate Oxide Shorts in CMOS Circuits. IEEE Trans. Computers 42(12): 1510-1516 (1993)
	1992
76		Siyad C. Ma, Edward J. McCluskey: Non-Conventional Faults in BiCMOS Digital Circuits. ITC 1992: 882-891
75		Nirmal R. Saxena, Piero Franco, Edward J. McCluskey: Simple Bounds on Serial Signature Analysis Aliasing for Random Testing. IEEE Trans. Computers 41(5): 638-645 (1992)
	1991
74		Nirmal R. Saxena, Piero Franco, Edward J. McCluskey: Bounds on Signature Analysis Aliasing for Random Testing. FTCS 1991: 104-113
73		Steven D. Millman, Edward J. McCluskey: Bridging, Transition, and Stuck-Open Faults in Self-Testing CMOS Checkers. FTCS 1991: 154-161
72		Hong Hao, Edward J. McCluskey: "Resistive Shorts" Within CMOS Gates. ITC 1991: 292-301
71		Kiyoshi Furuya, Edward J. McCluskey: Two-Pattern Test Capabilities of Autonomous TPG Circuits. ITC 1991: 704-711
70		Piero Franco, Edward J. McCluskey: Delay Testing of Digital Circuits by Output Waveform Analysis. ITC 1991: 798-807
69		Nirmal R. Saxena, Piero Franco, Edward J. McCluskey: Refined Bounds on Signature Analysis Aliasing for Random Testing. ITC 1991: 818-827
	1990
68		Steven D. Millman, Edward J. McCluskey, John M. Acken: Diagnosing CMOS bridging faults with stuck-at fault dictionaries. ITC 1990: 860-870
67		Edward J. McCluskey: Design Techniques for Testable Embedded Error Checkers. IEEE Computer 23(7): 84-88 (1990)
66		Nirmal R. Saxena, Edward J. McCluskey: Control-Flow Checking Using Watchdog Assists and Extended-Precision Checksums. IEEE Trans. Computers 39(4): 554-559 (1990)
65		Nirmal R. Saxena, Edward J. McCluskey: Analysis of Checksums, Extended-Precision Checksums, and Cyclic Redundancy Checks. IEEE Trans. Computers 39(7): 969-975 (1990)
	1989
64		Jon G. Jr. Udell, Edward J. McCluskey: Pseudo-exhaustive test and segmentation: formal definitions and extended fault coverage results. FTCS 1989: 292-298
63		Nirmal R. Saxena, Edward J. McCluskey: Control-flow checking using watchdog assists and extended-precision checksums. FTCS 1989: 428-435
	1988
62		Takashi Nanya, Samiha Mourad, Edward J. McCluskey: Multiple stuck-at fault testability of self-testing checkers. FTCS 1988: 381-386
61		Jon G. Udeli Jr., Edward J. McCluskey: Partial Hardware Partitioning: A New Pseudo-Exhaustive Test Implementation. ITC 1988: 1000
60		Edward J. McCluskey: Practice and Theory. ITC 1988: 203-204
59		Edward J. McCluskey, Fred Buelow: IC Quality and Test Transparency. ITC 1988: 295-301
58		Samy Makar, Edward J. McCluskey: On the Testing of Multiplexers. ITC 1988: 669-679
57		Steven D. Millman, Edward J. McCluskey: Detecting Bridging Faults with Stuck-at Test Sets. ITC 1988: 773-783
56		Samiha Mourad, Edward J. McCluskey: On Benchmarking Digital Testing Systems. ITC 1988: 997
55		Laung-Terng Wang, Edward J. McCluskey: Linear Feedback Shift Register Design Using Cyclic Codes. IEEE Trans. Computers 37(10): 1302-1306 (1988)
54		Aamer Mahmood, Edward J. McCluskey: Concurrent Error Detection Using Watchdog Processors - A Survey. IEEE Trans. Computers 37(2): 160-174 (1988)
53		Dick L. Liu, Edward J. McCluskey: Design of large embedded CMOS PLAs for built-in self-test. IEEE Trans. on CAD of Integrated Circuits and Systems 7(1): 50-59 (1988)
52		Edward J. McCluskey, Samy Makar, Samiha Mourad, Kenneth D. Wagner: Probability models for pseudorandom test sequences. IEEE Trans. on CAD of Integrated Circuits and Systems 7(1): 68-74 (1988)
51		Laung-Terng Wang, Edward J. McCluskey: Hybrid designs generating maximum-length sequences. IEEE Trans. on CAD of Integrated Circuits and Systems 7(1): 91-99 (1988)
50		Laung-Terng Wang, Edward J. McCluskey: Circuits for pseudoexhaustive test pattern generation. IEEE Trans. on CAD of Integrated Circuits and Systems 7(10): 1068-1080 (1988)
	1987
49		Hassanein H. Amer, Edward J. McCluskey: Modeling the Effect of Chip Failures on Cache Memory Systems. ICDE 1987: 340-346
48		Cary K. Chin, Edward J. McCluskey: Test Length for Pseudorandom Testing. IEEE Trans. Computers 36(2): 252-256 (1987)
47		Kenneth D. Wagner, Cary K. Chin, Edward J. McCluskey: Pseudorandom Testing. IEEE Trans. Computers 36(3): 332-343 (1987)
	1986
46		Edward J. McCluskey: Logic design principles - with emphasis on testable semicustom circuits. Prentice Hall 1986: I-XIX, 1-549
45		Samiha Mourad, Joseph L. A. Hughes, Edward J. McCluskey: Multiple Fault Detection in Parity Trees. COMPCON 1986: 441-444
44		Samiha Mourad, Joseph L. A. Hughes, Edward J. McCluskey: Stuck-At Fault Detection in Parity Trees. FJCC 1986: 836-840
43		Gregory Freeman, Dick L. Liu, Bruce A. Wooley, Edward J. McCluskey: Two CMOS Metastability Sensors. ITC 1986: 140-144
42		Laung-Terng Wang, Edward J. McCluskey: Circuits for Pseudo-Exhaustive Test Pattern Generation. ITC 1986: 25-37
41		Joseph L. A. Hughes, Edward J. McCluskey: Multiple Stuck-At Fault Coverage of Single Stuck-At Fault Test Sets. ITC 1986: 368-374
40		Laung-Terng Wang, Edward J. McCluskey: A Hybrid Design of Maximum-Length Sequence Generators. ITC 1986: 38-47
39		Mario L. Côrtes, Edward J. McCluskey: An Experiment on Intermittent-Failure Mechanisms. ITC 1986: 435-442
38		Laung-Terng Wang, Edward J. McCluskey: Condensed Linear Feedback Shift Register (LFSR) Testing - A Pseudoexhaustive Test Technique. IEEE Trans. Computers 35(4): 367-370 (1986)
37		Saied Bozorgui-Nesbat, Edward J. McCluskey: Lower Overhead Design for Testability of Programmable Logic Arrays. IEEE Trans. Computers 35(4): 379-383 (1986)
	1985
36		Edward J. McCluskey: Hardware Fault-Tolerance. COMPCON 1985: 260-263
35		Joseph L. A. Hughes, Samiha Mourad, Edward J. McCluskey: An Experimental Study Comparing 74LS181 Test Sets. COMPCON 1985: 384-387
34		Aamer Mahmood, Edward J. McCluskey, Aydin Ersoz: Concurrent System-Level Error Detection Using a Watchdog Processor. ITC 1985: 145-152
33		Edward J. McCluskey: Test Teaching. ITC 1985: 235
32		Cary K. Chin, Edward J. McCluskey: Test Length for Pseudo Random Testing. ITC 1985: 94-99
	1984
31		Syed Zahoor Hassan, Edward J. McCluskey: Pseudo-Exhaustive Testing of Sequential Machines Using Signature Analysis. ITC 1984: 320-326
30		Joseph L. A. Hughes, Edward J. McCluskey: An Analysis of the Multiple Fault Detection Capabilities of Single Stuck-at Fault Test Sets. ITC 1984: 52-58
29		Saied Bozorgui-Nesbat, Edward J. McCluskey: Lower Overhead Design for Testability of Programmable Logic Arrays. ITC 1984: 856-865
28		Edward J. McCluskey: Verification Testing - A Pseudoexhaustive Test Technique. IEEE Trans. Computers 33(6): 541-546 (1984)
27		Joseph L. A. Hughes, Edward J. McCluskey, David J. Lu: Design of Totally Self-Checking Comparators with an Arbitrary Number of Inputs. IEEE Trans. Computers 33(6): 546-550 (1984)
26		Javad Khakbaz, Edward J. McCluskey: Self-Testing Embedded Parity Checkers. IEEE Trans. Computers 33(8): 753-756 (1984)
25		David J. Lu, Edward J. McCluskey: Quantitative Evaluation of Self-Checking Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 3(2): 150-155 (1984)
	1983
24		Edward J. McCluskey: Teaching Testing. ITC 1983: 166-169
23		Aamer Mahmood, Edward J. McCluskey, David J. Lu: Concurrent Fault Detection Using a Watchdog Processor and Assertions. ITC 1983: 622-628
22		Edward J. McCluskey, David J. Lu: Recurrent Test Patterns. ITC 1983: 76-82
	1982
21		Edward J. McCluskey: Verification testing. DAC 1982: 495-500
20		Edward J. McCluskey: Built-In Verification Test. ITC 1982: 183-190
19		Ravishankar K. Iyer, Steven E. Butner, Edward J. McCluskey: A Statistical Failure/Load Relationship: Results of a Multicomputer Study. IEEE Trans. Computers 31(7): 697-706 (1982)
	1981
18		Edward J. McCluskey, Saied Bozorgui-Nesbat: Design for Autonomous Test. IEEE Trans. Computers 30(11): 866-875 (1981)
	1980
17		David J. Lu, Edward J. McCluskey, Masood Namjoo: Summary of Structural integrity Checking. IEEE Real-Time Systems Symposium 1980: 107-109
	1979
16		Edward J. McCluskey: Logic Design of Multivalued I2L Logic Circuits. IEEE Trans. Computers 28(8): 546-559 (1979)
	1978
15		Edward J. McCluskey, John F. Wakerly, E. David Crockett, Thomas E. Bredt, David J. Lu, William M. van Cleemput, Susan S. Owicki, Roy C. Ogus, Ravi Apte, M. Danielle Beaurdy, Jacques Losq: Proceedings of the 5th Annual Symposium on Computer Architecture, April 1978 ACM 1978
14		Edward J. McCluskey, Kenneth P. Parker, John J. Shedletsky: Boolean Network Probabilities and Network Design. IEEE Trans. Computers 27(2): 187-189 (1978)
13		Kenneth P. Parker, Edward J. McCluskey: Sequential Circuit Output Probabilities From Regular Expressions. IEEE Trans. Computers 27(3): 222-231 (1978)
	1977
12		Tich T. Dao, Edward J. McCluskey, Lewis K. Russel: Multivalued Integrated Injection Logic. IEEE Trans. Computers 26(12): 1233-1241 (1977)
	1975
11		Kenneth P. Parker, Edward J. McCluskey: Analysis of Logic Circuits with Faults Using Input Signal Probabilities. IEEE Trans. Computers 24(5): 573-578 (1975)
10		Kenneth P. Parker, Edward J. McCluskey: Probabilistic Treatment of General Combinational Networks. IEEE Trans. Computers 24(6): 668-670 (1975)
	1974
9		Dick B. Simmons, Edward J. McCluskey, Aaron Finerman, Michael L. Dertouzos, Jürg Nievergelt: University computer curricula. AFIPS National Computer Conference 1974: 1028
8		John F. Wakerly, Edward J. McCluskey: Design of Low-Cost General-Purpose Self-Diagnosing Computers. IFIP Congress 1974: 108-111
	1968
7		William F. Atchison, Samuel D. Conte, John W. Hamblen, Thomas E. Hull, Thomas A. Keenan, William B. Kehl, Edward J. McCluskey, Silvio O. Navarro, Werner C. Rheinboldt, Earl J. Schweppe, William Viavant, David M. Young: Curriculum 68: Recommendations for academic programs in computer science: a report of the ACM curriculum committee on computer science. Commun. ACM 11(3): 151-197 (1968)
	1964
6		J. F. Poage, Edward J. McCluskey: Derivation of optimum test sequences for sequential machines SWCT (FOCS) 1964: 121-132
	1963
5		Edward J. McCluskey: Logical design theory of NOR gate networks with no complemented inputs SWCT (FOCS) 1963: 137-148
4		Edward J. McCluskey: Reduction of Feedback Loops in Sequential Circuits and Carry Leads in Iterative Networks Information and Control 6(2): 99-118 (1963)
	1962
3		Edward J. McCluskey: Fundamental Mode and Pulse Mode Operations of Sequential Circuits. IFIP Congress 1962: 725-730
2		Edward J. McCluskey: Reduction of feedback loops in sequential circuits and carry leads in iterative networks SWCT (FOCS) 1962: 91-102
	1961
1		Edward J. McCluskey: Minimal sums for Boolean functions having many unspecified fundamental products SWCT (FOCS) 1961: 10-17

Coauthor Index

1	John M. Acken	[68]
2	Ahmad A. Al-Yamani	[144] [156] [157] [158] [159] [163] [166] [168] [169] [171] [181]
3	Hassanein H. Amer	[49]
4	Ravi Apte	[15]
5	William F. Atchison	[7]
6	LaNae J. Avra	[78] [109] [111] [116] [120]
7	M. Danielle Beaurdy	[15]
8	Daniel Boley	[86]
9	Saied Bozorgui-Nesbat	[18] [29] [37]
10	Kenneth A. Brand	[165]
11	Thomas E. Bredt	[15]
12	Fred Buelow	[59]
13	Steven E. Butner	[19]
14	Jonathan Chang	[100]
15	Jonathan T.-Y. Chang	[98] [102] [106] [112] [113] [114]
16	Ray Chen	[134]
17	Cary K. Chin	[32] [47] [48]
18	Erik Chmelar	[172] [176]
19	Kyoung Youn Cho	[170] [174] [175]
20	Yi-Chin Chu	[100] [112]
21	William M. van Cleemput	[15]
22	Samuel D. Conte	[7]
23	Mario L. Côrtes	[39]
24	E. David Crockett	[15]
25	Tich T. Dao	[12]
26	Scott Davidson	[133]
27	Michael L. Dertouzos	[9]
28	Stefan Eichenberger	[162]
29	Aydin Ersoz	[34]
30	William D. Farwell	[92] [100]
31	Philippe Faure	[164]
32	François-Fabien Ferhani	[163] [173] [178]
33	Santiago Fernández-Gomez	[121]
34	Aaron Finerman	[9]
35	Piero Franco	[69] [70] [74] [75] [91] [92] [100]
36	Gregory Freeman	[43]
37	Kiyoshi Furuya	[71] [84]
38	Gene H. Golub	[86]
39	John W. Hamblen	[7]
40	Hong Hao	[72] [77] [80]
41	Syed Zahoor Hassan	[31]
42	Wei-Je Huang	[121] [125] [130] [142] [145] [161]
43	Joseph L. A. Hughes	[27] [30] [35] [41] [44] [45]
44	Thomas E. Hull	[7]
45	Ravishankar K. Iyer (Ravi K. Iyer)	[19]
46	Thomas A. Keenan	[7]
47	William B. Kehl	[7]
48	Javad Khakbaz	[26]
49	Donghwi Lee	[176]
50	Jaekwang Lee	[177] [180]
51	Chien-Mo James Li (James Chien-Mo Li, J. C.-M. Li)	[114] [127] [135] [140] [153] [163] [167]
52	Edward Li	[163]
53	James Li	[150]
54	Dick L. Liu	[43] [53]
55	Jacques Losq	[15]
56	David J. Lu	[15] [17] [22] [23] [25] [27]
57	Siyad C. Ma	[76] [85] [91] [100]
58	Bob Madge	[151]
59	Aamer Mahmood	[23] [34] [54]
60	Samy Makar	[52] [58] [86] [88] [93] [108] [152]
61	Peter C. Maxwell	[151]
62	Steven D. Millman	[57] [68] [73]
63	Subhasish Mitra	[109] [111] [116] [119] [120] [121] [122] [123] [126] [129] [133] [136] [137] [141] [143] [145] [148] [149] [151] [152] [154] [155] [156] [157] [160] [161] [162] [163] [165] [166] [170] [175]
64	Samiha Mourad	[35] [44] [45] [52] [56] [62]
65	Shridhar K. Mukund	[89]
66	Masood Namjoo	[17]
67	Takashi Nanya	[62]
68	Silvio O. Navarro	[7]
69	Jürg Nievergelt	[9]
70	Phil Nigh	[134] [151] [178]
71	Robert B. Norwood	[96] [101] [107]
72	Roy C. Ogus	[15]
73	Nahmsuk Oh	[144] [146] [149]
74	Susan S. Owicki	[15]
75	Intaik Park	[169] [176] [177] [179]
76	Kenneth P. Parker	[10] [11] [13] [14]
77	J. F. Poage	[6]
78	Mike Purtell	[112] [114] [140]
79	T. R. N. Rao (Thammavarapu R. N. Rao)	[89]
80	Michel Renovell	[164]
81	Werner C. Rheinboldt	[7]
82	Mike Rodgers	[151]
83	Lewis K. Russel	[12]
84	Nirmal R. Saxena	[63] [65] [66] [69] [74] [75] [81] [86] [95] [105] [118] [119] [121] [123] [130] [131] [143] [148] [160] [161] [178]
85	Earl J. Schweppe	[7]
86	Seiji Seki	[84]
87	Xiaoping Shao	[124]
88	John J. Shedletsky	[14]
89	Philip P. Shirvani	[117]
90	Dick B. Simmons	[9]
91	Robert L. Stokes	[92] [100]
92	Mehdi Baradaran Tahoori	[154] [164]
93	Nur A. Touba	[82] [83] [87] [90] [97] [99] [103] [104] [110] [115] [132]
94	Shahin Toutounchi	[154]
95	Chao-Wen Tseng	[112] [114] [124] [128] [133] [134] [138] [140] [150] [163]
96	Jon G. Udeli Jr.	[61]
97	Jon G. Jr. Udell	[64]
98	William Viavant	[7]
99	Erik H. Volkerink	[162] [163] [165]
100	Kenneth D. Wagner	[47] [52]
101	John F. Wakerly	[8] [15]
102	Laung-Terng Wang	[38] [40] [42] [50] [51] [55]
103	Sanjay Wattal	[100] [112]
104	Bruce A. Wooley	[43]
105	David M. Wu	[124]
106	Teruhiko Yamada	[94]
107	Koji Yamazaki	[94]
108	David M. Young	[7]
109	Shu-Yi Yu	[121] [131] [139] [147] [161]
110	Chaohuang Zeng	[118]

Colors in the list of coauthors

Last update Sun Jun 3 16:06:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page