John V. McCanny

	2011
59		Ye Lu, John V. McCanny, Sakir Sezer: Generic Low-Latency NoC Router Architecture for FPGA Computing Systems. FPL 2011: 82-89
58		Ye Lu, John V. McCanny, Sakir Sezer: The Impact of Global Routing on the Performance of NoCs in FPGAs. ReConFig 2011: 369-374
57		Ye Lu, John V. McCanny, Sakir Sezer: Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip. SoCC 2011: 302-307
56		Lei Ma, Kevin Dickson, John McAllister, John V. McCanny: QR Decomposition-Based Matrix Inversion for High Performance Embedded MIMO Receivers. IEEE Transactions on Signal Processing 59(4): 1858-1867 (2011)
	2010
55		Ye Lu, Sakir Sezer, John V. McCanny: Advanced Multithreading Architecture with Hardware Based Scheduling. FPL 2010: 95-100
54		Ye Lu, Sakir Sezer, John V. McCanny: TLM2.0 based timing accurate modeling method for complex NoC systems. ISCAS 2010: 2900-2903
53		Ye Lu, Sakir Sezer, John V. McCanny: Design and analysis of an advanced static blocked multithreading architecture. SoCC 2010: 169-173
52		Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns: High-Performance random data lookup for network processing. SoCC 2010: 272-277
51		Liang Lu, John V. McCanny, Sakir Sezer: Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding. IET Computers & Digital Techniques 4(5): 349-364 (2010)
50		Yingxi Lu, Máire O'Neill, John V. McCanny: Evaluation of Random Delay Insertion against DPA on FPGAs. TRETS 4(1): 11 (2010)
	2009
49		Yingxi Lu, Keanhong Boey, Máire O'Neill, John V. McCanny, Akashi Satoh: Is the differential frequency-based attack effective against random delay insertion? SiPS 2009: 051-056
48		Yongping Liu, Sakir Sezer, John V. McCanny: NFA decomposition and multiprocessing architecture for parallel regular expression processing. SoCC 2009: 347-350
47		Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns: DDR3 based lookup circuit for high-performance network processing. SoCC 2009: 351-354
46		Liang Lu, John V. McCanny, Sakir Sezer: Subpixel Interpolation Architecture for Multistandard Video Motion Estimation. IEEE Trans. Circuits Syst. Video Techn. 19(12): 1897-1901 (2009)
	2008
45		Lei Ma, Kevin Dickson, John McAllister, John V. McCanny: Modified givens rotations and their application to matrix inversion. ICASSP 2008: 1437-1440
44		Yingxi Lu, Máire O'Neill, John V. McCanny: Differential Power Analysis of a SHACAL-2 hardware implementation. ISCAS 2008: 2933-2936
43		Lei Ma, Kevin Dickson, John McAllister, John V. McCanny, Mathini Sellathurai: Reduced-complexity MSGR-based matrix inversion. SiPS 2008: 124-128
42		Liang Lu, John V. McCanny, Sakir Sezer: Multi-standard sub-pixel interpolation architecture for video Motion Estimation. SoCC 2008: 229-232
41		Xin Yang, Jun Mu, Sakir Sezer, John V. McCanny, Earl E. Swartzlander Jr.: High performance IP lookup circuit using DDR SDRAM. SoCC 2008: 371-374
40		Yen-Kuang Chen, David W. Lin, John V. McCanny, Edwin Hsing-Mean Sha: Guest Editorial: Special Issue on Design and Programming of Signal Processors for Multimedia Communication. Signal Processing Systems 51(3): 207-208 (2008)
39		Roger F. Woods, John V. McCanny, John G. McWhirter: From Bit Level Systolic Arrays to HDTV Processor Chips. Signal Processing Systems 53(1-2): 35-49 (2008)
	2007
38		Liang Lu, John V. McCanny, Sakir Sezer: Systolic Array Based Architecture for Variable Block-Size Motion Estimation. AHS 2007: 160-168
37		Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns: Novel Content Addressable Memory Architecture for Adaptive Systems. AHS 2007: 633-640
36		Liang Lu, John V. McCanny, Sakir Sezer: Reconfigurable Motion Estimation Architecture for Multi-standard Video Compression. ASAP 2007: 253-259
35		Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns: A versatile content addressable memory architecture. SoCC 2007: 215-218
34		Liang Lu, John V. McCanny, Sakir Sezer: Reconfigurable video motion estimation processor. SoCC 2007: 55-58
	2006
33		Friederich Kupzog, Holger Blume, Tobias G. Noll, Kieran McLaughlin, Sakir Sezer, John V. McCanny: Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup. AICT/ICIW 2006: 56
32		John V. McCanny, Roger F. Woods, John G. McWhirter: From Bit Level Systolic Arrays to HDTV Processor Chips. ASAP 2006: 159-162
31		Neil Smyth, Máire McLoone, John V. McCanny: An Adaptable And Scalable Asymmetric Cryptographic Processor. ASAP 2006: 341-346
30		Kieran McLaughlin, Friederich Kupzog, Holger Blume, Sakir Sezer, Tobias G. Noll, John V. McCanny: Design and analysis of matching circuit architectures for a closest match lookup. IPDPS 2006
	2005
29		Ciaran McIvor, Máire McLoone, John V. McCanny: High-Radix Systolic Modular Multiplication on Reconfigurable Hardware. FPT 2005: 13-18
	2004
28		Ciaran McIvor, Máire McLoone, John V. McCanny: FPGA Montgomery Multiplier Architectures - A Comparison. FCCM 2004: 279-282
27		Ciaran McIvor, Máire McLoone, John V. McCanny: FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p). ISCAS (3) 2004: 509-512
	2003
26		Zhaohui Liu, Kevin Dickson, John V. McCanny: A floating-point CORDIC based SVD processor. ASAP 2003: 194-203
25		Swee Yeow, John V. McCanny: A VLSI Architecture for Advanced Video Coding Motion Estimation. ASAP 2003: 293-
24		Máire McLoone, John V. McCanny: Very High Speed 17 Gbps SHACAL Encryption Architecture. FPL 2003: 111-120
23		Ciaran McIvor, Máire McLoone, John V. McCanny: A high-speed, low latency RSA decryption silicon core. ISCAS (4) 2003: 133-136
22		Máire McLoone, John V. McCanny: Rijndael FPGA Implementations Utilising Look-Up Tables. VLSI Signal Processing 34(3): 261-275 (2003)
	2002
21		Paul V. McCanny, Shahid Masud, John V. McCanny: Design and implementation of the symmetrically extended 2-D Wavelet Transform. ICASSP 2002: 3108-3111
20		Kok Sing Yap, John V. McCanny: A hybrid mixed cost-function TEQ initialization algorithm for ADSL modems. ICASSP 2002: 4183
	2001
19		Máire McLoone, John V. McCanny: High Performance Single-Chip FPGA Rijndael Algorithm Implementations. CHES 2001: 65-76
18		Máire McLoone, John V. McCanny: Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm. FPL 2001: 152-161
17		Paul V. McCanny, Shahid Masud, John V. McCanny: An efficient architecture for the 2-D biorthogonal discrete wavelet transform. ICIP (3) 2001: 314-317
16		Shahid Masud, John V. McCanny: Design of Silicon IP Cores for Biorthogonal Wavelet Transforms. VLSI Signal Processing 29(3): 179-196 (2001)
	2000
15		Robert Hamill, John V. McCanny, Richard L. Walke: Online CORDIC algorithm and VLSI architecture for implementing QR-array processors. IEEE Transactions on Signal Processing 48(2): 592-598 (2000)
14		Gaye Lightbody, Richard L. Walke, Roger Woods, John V. McCanny: Linear QR Architecture for a Single Chip Adaptive Beamformer. VLSI Signal Processing 24(1): 67-81 (2000)
	1998
13		Shahid Masud, John V. McCanny: Rapid Design of Discrete Orthonormal Wavelet Transforms. International Workshop on Rapid System Prototyping 1998: 142-
	1997
12		David W. Trainor, Roger F. Woods, John V. McCanny: Architectural Synthesis of Digital Signal Processing Algorithms Using "IRIS". VLSI Signal Processing 16(1): 41-55 (1997)
	1996
11		Colin C. W. Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods: A New FFT Architecture and Chip Design for Motion Compensation based on Phase Correlation. ASAP 1996: 83-92
	1995
10		Stephen E. McQuillan, John V. McCanny: A Systematic Methodology for the Design of High Performance Recursive Digital Filters. IEEE Trans. Computers 44(8): 971-982 (1995)
9		M. Yan, John V. McCanny, Y. Hu: VLSI architectures for vector quantization. VLSI Signal Processing 10(1): 5-23 (1995)
	1994
8		Stephen E. McQuillan, John V. McCanny: Fast VLSI algorithms for division and square root. VLSI Signal Processing 8(2): 151-168 (1994)
	1993
7		Stephen E. McQuillan, John V. McCanny, Robert Hamill: New algorithms and VLSI architectures for SRT division and square root. IEEE Symposium on Computer Arithmetic 1993: 80-86
	1992
6		M. Yan, John V. McCanny: Systolic inner product arrays with automatic word rounding. VLSI Signal Processing 4(2-3): 227-242 (1992)
5		Rajinder Jit Singh, John V. McCanny: High performance VLSI architecture for Wave Digital Filtering. VLSI Signal Processing 4(4): 269-278 (1992)
	1991
4		John V. McCanny: On the use of most significant digit first arithmetic in the design of high performance DSP chips. Algorithms and Parallel VLSI Architectures 1991: 243-260
3		O. C. McNally, John V. McCanny, Roger F. Woods: Design of a Highly Pipelined 2nd Order IIR Filter Chip. VLSI 1991: 19-28
	1990
2		M. Yan, John V. McCanny: A bit-level systolic architecture for implementing a VQ tree search. VLSI Signal Processing 2(3): 149-158 (1990)
	1989
1		S. C. Knowles, John G. McWhirter, Roger F. Woods, John V. McCanny: Bit-Level systolic architectures for high performance IIR filtering. VLSI Signal Processing 1(1): 9-24 (1989)

Coauthor Index

1	Holger Blume	[30] [33]
2	Keanhong Boey	[49]
3	Dwayne Burns	[35] [37] [47] [52]
4	Yen-Kuang Chen	[40]
5	Kevin Dickson	[26] [43] [45] [56]
6	Tiong Jiu Ding	[11]
7	Robert Hamill	[7] [15]
8	Y. Hu	[9]
9	Colin C. W. Hui	[11]
10	S. C. Knowles	[1]
11	Friederich Kupzog	[30] [33]
12	Gaye Lightbody	[14]
13	David W. Lin	[40]
14	Yongping Liu	[48]
15	Zhaohui Liu	[26]
16	Liang Lu	[34] [36] [38] [42] [46] [51]
17	Ye Lu	[53] [54] [55] [57] [58] [59]
18	Yingxi Lu	[44] [49] [50]
19	Lei Ma	[43] [45] [56]
20	Shahid Masud	[13] [16] [17] [21]
21	John McAllister	[43] [45] [56]
22	Paul V. McCanny	[17] [21]
23	Ciaran McIvor	[23] [27] [28] [29]
24	Kieran McLaughlin	[30] [33]
25	O. C. McNally	[3]
26	Stephen E. McQuillan	[7] [8] [10]
27	John G. McWhirter	[1] [32] [39]
28	Jun Mu	[41]
29	Tobias G. Noll	[30] [33]
30	Máire O'Neill (Máire McLoone)	[18] [19] [22] [23] [24] [27] [28] [29] [31] [44] [49] [50]
31	Akashi Satoh	[49]
32	Mathini Sellathurai	[43]
33	Sakir Sezer	[30] [33] [34] [35] [36] [37] [38] [41] [42] [46] [47] [48] [51] [52] [53] [54] [55] [57] [58] [59]
34	Edwin Hsing-Mean Sha	[40]
35	Rajinder Jit Singh	[5]
36	Neil Smyth	[31]
37	Earl E. Swartzlander Jr.	[41]
38	David W. Trainor	[12]
39	Richard L. Walke	[14] [15]
40	Roger Woods (Roger F. Woods)	[1] [3] [11] [12] [14] [32] [39]
41	M. Yan	[2] [6] [9]
42	Xin Yang	[35] [37] [41] [47] [52]
43	Kok Sing Yap	[20]
44	Swee Yeow	[25]

Colors in the list of coauthors

Last update Mon Jun 4 20:40:43 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page