Philippe Maurine

	2012
66		Pierre Bayon, Lilian Bossuet, Alain Aubert, Viktor Fischer, François Poucheret, Bruno Robisson, Philippe Maurine: Contactless Electromagnetic Active Attack on Ring Oscillator Based True Random Number Generator. COSADE 2012: 151-166
65		Guilherme Perin, Lionel Torres, Pascal Benoit, Philippe Maurine: Amplitude demodulation-based EM analysis of different RSA implementations. DATE 2012: 1167-1172
64		Amine Dehbaoui, Jean-Max Dutertre, Bruno Robisson, P. Orsatelli, Philippe Maurine, Assia Tria: Injection of transient faults using electromagnetic pulses -Practical results on a cryptographic system-. IACR Cryptology ePrint Archive 2012: 123 (2012)
63		Sébastien Tiran, Philippe Maurine: Magnitude Squared Coherence based SCA. IACR Cryptology ePrint Archive 2012: 77 (2012)
62		Amine Dehbaoui, Victor Lomné, Thomas Ordas, Lionel Torres, Michel Robert, Philippe Maurine: Enhancing Electromagnetic Analysis Using Magnitude Squared Incoherence. IEEE Trans. VLSI Syst. 20(3): 573-577 (2012)
61		Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme: Delay-correlation-aware SSTA based on conditional moments. Microelectronics Journal 43(4): 263-273 (2012)
	2011
60		François Poucheret, Karim Tobich, Mathieu Lisart, Laurent Chusseau, Bruno Robisson, Philippe Maurine: Local and Direct EM Injection of Power Into CMOS Integrated Circuits. FDTC 2011: 100-104
59		Florent Bruguier, Pascal Benoit, Philippe Maurine, Lionel Torres: A New Process Characterization Method for FPGAs Based on Electromagnetic Analysis. FPL 2011: 20-23
58		Bruno Vaquie, Sébastien Tiran, Philippe Maurine: A Secure D Flip-Flop against Side Channel Attacks. PATMOS 2011: 331-340
57		Amine Dehbaoui, Sébastien Tiran, Philippe Maurine, François-Xavier Standaert, Nicolas Veyrat-Charvillon: Spectral Coherence Analysis - First Experimental Results -. IACR Cryptology ePrint Archive 2011: 56 (2011)
56		Rafael Iankowski Soares, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Philippe Maurine, Lionel Torres: A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines. IEEE Design & Test of Computers 28(5): 62-71 (2011)
55		Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard: Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization. Microelectronics Journal 42(5): 718-732 (2011)
	2010
54		Victor Lomné, Amine Dehbaoui, Philippe Maurine, Lionel Torres, Michel Robert: Differential Power Analysis enhancement with statistical preprocessing. DATE 2010: 1301-1304
53		Victor Lomné, Philippe Maurine, Lionel Torres, Thomas Ordas, Mathieu Lisart, Jérome Toublanc: Modeling Time Domain Magnetic Emissions of ICs. PATMOS 2010: 238-249
52		Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Amine Dehbaoui, Philippe Maurine, Lionel Torres: A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks. SBCCI 2010: 115-120
51		François Poucheret, Lyonel Barthe, Pascal Benoit, Lionel Torres, Philippe Maurine, Michel Robert: Spatial EM jamming: A countermeasure against EM Analysis? VLSI-SoC 2010: 105-110
50		Nabila Moubdi, Philippe Maurine, Robin Wilson, Sylvain Engels, Nadine Azémard, Vincent Dumettier, Pierre Busson: On-Chip Process Variability Monitoring Flow. J. Low Power Electronics 6(4): 601-606 (2010)
	2009
49		Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans: Evaluation on FPGA of triple rail logic robustness against DPA and DEMA. DATE 2009: 634-639
48		Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme: Interpreting SSTA Results with Correlation. PATMOS 2009: 16-25
47		Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azémard, Vincent Dumettier, Abhishek Bansal, Sebastien Barasinski, Alain Tournier, Guy Durieu, David Meyer, Pierre Busson, Sarah Verhaeren, Sylvain Engels: Product On-Chip Process Compensation for Low Power and Yield Enhancement. PATMOS 2009: 247-255
46		Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard: Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities. PATMOS 2009: 266-275
45		Amine Dehbaoui, Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert: Enhancing Electromagnetic Attacks Using Spectral Coherence Based Cartography. VLSI-SoC 2009: 135-155
44		V. Migairou, Robin Wilson, Sylvain Engels, Zequin Wu, Nadine Azémard, Philippe Maurine: Timing margin evaluation with a simple statistical timing analysis flow. J. Embedded Computing 3(3): 221-229 (2009)
	2008
43		Michael Yap San Min, Philippe Maurine, Magali Bastian, Michel Robert: A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM. DELTA 2008: 107-110
42		Michael Yap San Min, Philippe Maurine, Magali Bastian, Michel Robert: Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects. ISVLSI 2008: 310-315
41		Bettina Rebaud, Marc Belleville, Christian Bernard, Zequin Wu, Michel Robert, Philippe Maurine, Nadine Azémard: Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. ISVLSI 2008: 316-321
40		Thomas Ordas, Mathieu Lisart, Etienne Sicard, Philippe Maurine, Lionel Torres: Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits. PATMOS 2008: 229-236
39		Victor Lomné, Thomas Ordas, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans: Triple Rail Logic Robustness against DPA. ReConFig 2008: 415-420
38		Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert: Evaluating the robustness of secure triple track logic through prototyping. SBCCI 2008: 193-198
37		Nadine Azémard, Philippe Maurine, Johan Vounckx: Editorial. Integration 41(1): 1 (2008)
	2007
36		B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine: Temperature and voltage aware timing analysis: application to voltage drops. DATE 2007: 1012-1017
35		V. Migairou, Robin Wilson, Sylvain Engels, Zequin Wu, Nadine Azémard, Philippe Maurine: A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation. PATMOS 2007: 138-147
34		Alin Razafindraibe, Michel Robert, Philippe Maurine: Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA. PATMOS 2007: 340-351
33		Alin Razafindraibe, Philippe Maurine: A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates. PATMOS 2007: 394-403
32		Alin Razafindraibe, Michel Robert, Philippe Maurine: Improvement of dual rail logic as a countermeasure against DPA. VLSI-SoC 2007: 270-275
31		Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne: Low Power Oriented CMOS Circuit Optimization Protocol CoRR abs/0710.4760: (2007)
30		B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine: Temperature- and Voltage-Aware Timing Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 801-815 (2007)
	2006
29		Johan Vounckx, Nadine Azémard, Philippe Maurine: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings Springer 2006
28		Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard: Circuit sizing method under delay constraint. ISCAS 2006
27		B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine: Timing analysis in presence of supply voltage and temperature variations. ISPD 2006: 10-16
26		V. Migairou, Robin Wilson, Sylvain Engels, Nadine Azémard, Philippe Maurine: Statistical Characterization of Library Timing Performance. PATMOS 2006: 468-476
25		Alin Razafindraibe, Michel Robert, Philippe Maurine: Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks. PATMOS 2006: 634-644
24		Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin: Security evaluation of dual rail logic against DPA attacks. VLSI-SoC 2006: 181-186
23		B. Lasbouygues, Sylvain Engels, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Logical effort model extension to propagation delay representation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1677-1684 (2006)
22		Sylvain Engels, Robin Wilson, Nadine Azémard, Philippe Maurine: A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects. Integration 39(4): 433-456 (2006)
	2005
21		Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne: Low Power Oriented CMOS Circuit Optimization Protocol. DATE 2005: 640-645
20		Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine: A Method to Design Compact Dual-rail Asynchronous Primitives. PATMOS 2005: 571-580
19		Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard: Speed Indicators for Circuit Optimization. PATMOS 2005: 618-628
18		B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine: Temperature Dependency in UDSM Process. PATMOS 2005: 693-703
17		Alin Razafindraibe, Michel Robert, Philippe Maurine: Compact and Secured Primitives for the Design of Asynchronous Circuits. J. Low Power Electronics 1(1): 20-26 (2005)
	2004
16		Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Delay bound based CMOS gate sizing technique. ISCAS (5) 2004: 189-192
15		Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Performance Metric Based Optimization Protocol. PATMOS 2004: 100-109
14		B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Temperature Dependence in Low Power CMOS UDSM Process. PATMOS 2004: 110-118
13		A. Landrault, Nadine Azémard, Philippe Maurine, Michel Robert, Daniel Auvergne: Design Optimization with Automated Cell Generation. PATMOS 2004: 722-731
12		B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Physical Extension of the Logical Effort Model. PATMOS 2004: 838-848
	2003
11		Philippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin: Statistic Implementation of QDI Asynchronous Primitives. PATMOS 2003: 181-191
10		Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne: Metric Definition for Circuit Speed Optimization. PATMOS 2003: 451-460
9		Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne: CMOS Gate Sizing under Delay Constraint. PATMOS 2003: 60-69
	2002
8		Philippe Maurine, Xavier Michel, Nadine Azémard, Daniel Auvergne: Gate speed improvement at minimal power dissipation. APCCAS (2) 2002: 325-330
7		Philippe Maurine, Nadine Azémard, Daniel Auvergne: Structure Independent Representation of Output Transition Time for CMOS Library. PATMOS 2002: 247-257
6		Philippe Maurine, Mustapha Rezzoug, Nadine Azémard, Daniel Auvergne: Transition time modeling in deep submicron CMOS. IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1352-1363 (2002)
	2001
5		Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne: Output transition time modeling of CMOS structures. ISCAS (5) 2001: 363-366
4		Philippe Maurine, Nadine Azémard, Daniel Auvergne: Gate Sizing for Low Power Design. VLSI-SOC 2001: 301-312
3		Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne: Feasible Delay Bound Definition. VLSI-SOC 2001: 325-335
	2000
2		Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne: Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design. PATMOS 2000: 129-138
1		Mustapha Rezzoug, Philippe Maurine, Daniel Auvergne: Second Generation Delay Model for Submicron CMOS Process. PATMOS 2000: 159-167

Coauthor Index

1	M. Aline	[3]
2	Alain Aubert	[66]
3	Daniel Auvergne	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [12] [13] [14] [15] [16] [21] [23] [31]
4	Nadine Azémard (Nadine Azémard-Crestani)	[3] [4] [6] [7] [8] [9] [10] [12] [13] [14] [15] [16] [18] [19] [21] [22] [23] [26] [27] [28] [29] [30] [31] [35] [36] [37] [41] [44] [46] [47] [48] [50] [55] [61]
5	Abhishek Bansal	[47]
6	Sebastien Barasinski	[47]
7	Lyonel Barthe	[51]
8	Magali Bastian (Magali Bastian Hage-Hassan)	[42] [43]
9	Pierre Bayon	[66]
10	Edith Beigné	[46] [55]
11	Marc Belleville	[41] [46] [55]
12	Pascal Benoit	[51] [59] [65]
13	Christian Bernard	[41] [46] [55]
14	Lilian Bossuet	[66]
15	G. Fraidy Bouesse	[11]
16	Florent Bruguier	[59]
17	Pierre Busson	[47] [50]
18	Ney Laert Vilar Calazans (Ney Calazans)	[38] [39] [49] [52] [56]
19	Laurent Chusseau	[60]
20	Amine Dehbaoui	[45] [52] [54] [57] [62] [64]
21	Gilles R. Ducharme	[48] [61]
22	Vincent Dumettier	[47] [50]
23	Guy Durieu	[47]
24	Jean-Max Dutertre	[64]
25	Sylvain Engels	[22] [23] [26] [35] [44] [47] [50]
26	Viktor Fischer	[66]
27	A. Landrault	[13] [19] [28]
28	B. Lasbouygues	[12] [14] [18] [23] [27] [30] [36]
29	Mathieu Lisart	[40] [53] [60]
30	Victor Lomné	[38] [39] [45] [49] [52] [53] [54] [62]
31	David Meyer	[47]
32	Xavier Michel	[8] [9] [10] [15] [16] [21] [31]
33	V. Migairou	[26] [35] [44]
34	Michael Yap San Min	[42] [43]
35	Fernando Gehm Moraes (Fernando Moraes)	[56]
36	Nabila Moubdi	[47] [50]
37	Thomas Ordas	[39] [40] [53] [62]
38	P. Orsatelli	[64]
39	Guilherme Perin	[65]
40	François Poucheret	[51] [60] [66]
41	Alin Razafindraibe	[17] [20] [24] [25] [32] [33] [34]
42	Bettina Rebaud	[41] [46] [55]
43	Marc Renaudin	[11] [20] [24]
44	Mustapha Rezzoug	[1] [2] [5] [6]
45	Jean-Baptiste Rigaud	[11]
46	Michel Robert	[13] [17] [20] [24] [25] [32] [34] [38] [39] [41] [42] [43] [45] [46] [49] [51] [54] [55] [62]
47	Bruno Robisson	[60] [64] [66]
48	Etienne Sicard	[40]
49	Gilles Sicard	[11]
50	Rafael Soares (Rafael Iankowski Soares)	[38] [39] [49] [52] [56]
51	François-Xavier Standaert	[57]
52	Sébastien Tiran	[57] [58] [63]
53	Karim Tobich	[60]
54	Lionel Torres	[38] [39] [40] [45] [49] [51] [52] [53] [54] [56] [59] [62] [65]
55	Jérome Toublanc	[53]
56	Alain Tournier	[47]
57	Assia Tria	[64]
58	Bruno Vaquie	[58]
59	Sarah Verhaeren	[47]
60	Alexandre Verle	[9] [10] [15] [16] [19] [21] [28] [31]
61	Nicolas Veyrat-Charvillon	[57]
62	Johan Vounckx	[29] [37]
63	Robin Wilson	[12] [14] [18] [22] [23] [26] [27] [30] [35] [36] [44] [47] [50]
64	Zeqin Wu	[48] [61]
65	Zequin Wu	[35] [41] [44]

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